Fix MEMR status not set during halt acknowledge
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@ -53,7 +53,7 @@ impl MemCycle {
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Self::In(_) => Status::WO | Status::INP,
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Self::In(_) => Status::WO | Status::INP,
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Self::Out(_, _) => Status::OUT,
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Self::Out(_, _) => Status::OUT,
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Self::Inta(_) => Status::INTA | Status::WO | Status::M1,
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Self::Inta(_) => Status::INTA | Status::WO | Status::M1,
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Self::Hlta => Status::HLTA | Status::WO | Status::M1,
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Self::Hlta => Status::HLTA | Status::WO | Status::M1 | Status::MEMR,
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Self::IntaHlt(_) => Status::INTA | Status::HLTA | Status::WO | Status::M1,
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Self::IntaHlt(_) => Status::INTA | Status::HLTA | Status::WO | Status::M1,
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}
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}
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}
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}
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