stuff
This commit is contained in:
pjht
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commit
fa95233f10
501
ASync Serial.circ
Normal file
501
ASync Serial.circ
Normal file
@ -0,0 +1,501 @@
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||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="2.7.1" version="1.0">
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This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<lib desc="#Wiring" name="0">
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<tool name="Splitter">
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<a name="facing" val="north"/>
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<a name="fanout" val="32"/>
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<a name="incoming" val="32"/>
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</tool>
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<tool name="Pin">
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<a name="tristate" val="false"/>
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<a name="pull" val="down"/>
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<a name="label" val="Takeover"/>
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</tool>
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<tool name="Probe">
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<a name="radix" val="16"/>
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<a name="label" val="mem out"/>
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</tool>
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<tool name="Tunnel">
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<a name="label" val="pop"/>
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</tool>
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<tool name="Constant">
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<a name="value" val="0x0"/>
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</tool>
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</lib>
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<lib desc="#Gates" name="1">
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<tool name="Controlled Buffer">
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<a name="facing" val="west"/>
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</tool>
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</lib>
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<lib desc="#Plexers" name="2"/>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4">
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<tool name="ROM">
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<a name="contents">addr/data: 8 8
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0
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</a>
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</tool>
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</lib>
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<lib desc="#I/O" name="5"/>
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<lib desc="#Base" name="6">
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<tool name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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</lib>
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<main name="main"/>
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<options>
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<a name="gateUndefined" val="ignore"/>
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<a name="simlimit" val="1000"/>
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<a name="simrand" val="0"/>
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</options>
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<mappings>
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<tool lib="6" map="Button2" name="Menu Tool"/>
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<tool lib="6" map="Button3" name="Menu Tool"/>
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<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="6" name="Poke Tool"/>
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<tool lib="6" name="Edit Tool"/>
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<tool lib="6" name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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<sep/>
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<tool lib="0" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="RPLoad"/>
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</tool>
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<tool lib="0" name="Pin">
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="label" val="SPout"/>
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</tool>
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<tool lib="1" name="NOT Gate">
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<a name="facing" val="north"/>
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</tool>
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<tool lib="1" name="AND Gate">
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<a name="size" val="30"/>
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<a name="inputs" val="2"/>
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<a name="negate1" val="true"/>
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</tool>
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<tool lib="1" name="OR Gate">
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<a name="facing" val="west"/>
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<a name="size" val="30"/>
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<a name="inputs" val="2"/>
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</tool>
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</toolbar>
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<circuit name="Sender">
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<a name="circuit" val="Sender"/>
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<a name="clabel" val=""/>
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<a name="clabelup" val="east"/>
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<a name="clabelfont" val="SansSerif plain 12"/>
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<wire from="(100,270)" to="(120,270)"/>
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<wire from="(420,190)" to="(420,310)"/>
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<wire from="(210,340)" to="(210,410)"/>
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<wire from="(290,300)" to="(300,300)"/>
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<wire from="(40,120)" to="(210,120)"/>
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<wire from="(130,260)" to="(150,260)"/>
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<wire from="(210,410)" to="(380,410)"/>
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<wire from="(150,370)" to="(290,370)"/>
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<wire from="(370,310)" to="(370,380)"/>
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<wire from="(320,270)" to="(400,270)"/>
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<wire from="(370,380)" to="(380,380)"/>
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<wire from="(380,380)" to="(390,380)"/>
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<wire from="(400,390)" to="(400,430)"/>
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<wire from="(230,40)" to="(230,120)"/>
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<wire from="(250,300)" to="(280,300)"/>
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<wire from="(250,230)" to="(250,240)"/>
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<wire from="(380,380)" to="(380,410)"/>
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<wire from="(120,270)" to="(120,320)"/>
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<wire from="(80,250)" to="(90,250)"/>
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<wire from="(40,530)" to="(410,530)"/>
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<wire from="(350,280)" to="(350,300)"/>
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<wire from="(420,380)" to="(520,380)"/>
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<wire from="(80,270)" to="(100,270)"/>
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<wire from="(90,250)" to="(90,280)"/>
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<wire from="(370,310)" to="(420,310)"/>
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<wire from="(300,290)" to="(300,300)"/>
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<wire from="(250,200)" to="(250,220)"/>
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<wire from="(320,260)" to="(320,270)"/>
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<wire from="(260,270)" to="(260,280)"/>
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<wire from="(280,300)" to="(280,320)"/>
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<wire from="(120,180)" to="(210,180)"/>
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<wire from="(290,430)" to="(400,430)"/>
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<wire from="(340,300)" to="(350,300)"/>
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<wire from="(140,190)" to="(420,190)"/>
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<wire from="(260,270)" to="(290,270)"/>
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<wire from="(410,390)" to="(410,530)"/>
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<wire from="(290,300)" to="(290,370)"/>
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<wire from="(270,280)" to="(310,280)"/>
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<wire from="(110,200)" to="(250,200)"/>
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<wire from="(140,250)" to="(150,250)"/>
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<wire from="(160,220)" to="(160,240)"/>
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<wire from="(290,260)" to="(290,270)"/>
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<wire from="(90,250)" to="(130,250)"/>
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<wire from="(100,200)" to="(110,200)"/>
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<wire from="(270,280)" to="(270,330)"/>
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<wire from="(520,120)" to="(520,380)"/>
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<wire from="(280,320)" to="(440,320)"/>
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<wire from="(310,270)" to="(310,280)"/>
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<wire from="(240,10)" to="(420,10)"/>
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<wire from="(140,190)" to="(140,250)"/>
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<wire from="(250,230)" to="(300,230)"/>
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<wire from="(120,320)" to="(240,320)"/>
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<wire from="(210,340)" to="(240,340)"/>
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<wire from="(250,280)" to="(260,280)"/>
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<wire from="(290,260)" to="(300,260)"/>
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<wire from="(230,120)" to="(520,120)"/>
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<wire from="(290,430)" to="(290,440)"/>
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<wire from="(100,220)" to="(110,220)"/>
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<wire from="(320,270)" to="(320,290)"/>
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<wire from="(310,280)" to="(350,280)"/>
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<wire from="(290,370)" to="(290,430)"/>
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<wire from="(210,40)" to="(210,120)"/>
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<wire from="(130,250)" to="(130,260)"/>
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<wire from="(120,180)" to="(120,270)"/>
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<wire from="(150,270)" to="(150,370)"/>
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<wire from="(110,220)" to="(160,220)"/>
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<wire from="(210,120)" to="(210,180)"/>
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<wire from="(420,10)" to="(420,190)"/>
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<wire from="(40,120)" to="(40,530)"/>
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<wire from="(240,440)" to="(290,440)"/>
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<comp lib="0" loc="(110,220)" name="Pull Resistor">
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<a name="facing" val="north"/>
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</comp>
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<comp lib="1" loc="(310,300)" name="NOT Gate">
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<a name="facing" val="west"/>
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</comp>
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<comp lib="0" loc="(100,200)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="Pin"/>
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</comp>
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<comp lib="0" loc="(220,450)" name="Splitter"/>
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<comp lib="0" loc="(250,220)" name="Splitter">
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<a name="facing" val="south"/>
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<a name="fanout" val="8"/>
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<a name="incoming" val="8"/>
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<a name="appear" val="right"/>
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</comp>
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<comp lib="0" loc="(80,250)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="Sin"/>
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</comp>
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<comp lib="4" loc="(420,370)" name="Counter">
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<a name="width" val="4"/>
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<a name="max" val="0x8"/>
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<a name="ongoal" val="stay"/>
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</comp>
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<comp lib="1" loc="(320,260)" name="Controlled Buffer"/>
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<comp lib="0" loc="(200,470)" name="Clock">
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<a name="facing" val="north"/>
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</comp>
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<comp lib="4" loc="(220,450)" name="Counter">
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<a name="width" val="2"/>
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<a name="max" val="0x3"/>
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</comp>
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<comp lib="1" loc="(320,290)" name="Controlled Buffer"/>
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<comp lib="4" loc="(150,260)" name="Shift Register">
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<a name="length" val="9"/>
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</comp>
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<comp lib="0" loc="(100,220)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="Pload"/>
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</comp>
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<comp lib="0" loc="(250,300)" name="Splitter">
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<a name="facing" val="north"/>
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<a name="fanout" val="8"/>
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<a name="incoming" val="8"/>
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</comp>
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<comp lib="0" loc="(300,230)" name="Constant">
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<a name="facing" val="west"/>
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<a name="value" val="0x0"/>
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</comp>
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<comp lib="0" loc="(400,270)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="label" val="Sout"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(110,200)" name="Pull Resistor"/>
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<comp lib="0" loc="(80,270)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="Trans"/>
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</comp>
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<comp lib="0" loc="(440,320)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="label" val="Pout"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="4" loc="(240,10)" name="D Flip-Flop"/>
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<comp lib="0" loc="(90,280)" name="Pull Resistor">
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<a name="facing" val="north"/>
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</comp>
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<comp lib="1" loc="(270,330)" name="OR Gate">
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<a name="size" val="30"/>
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<a name="inputs" val="2"/>
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</comp>
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<comp lib="0" loc="(100,270)" name="Pull Resistor">
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<a name="facing" val="north"/>
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</comp>
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</circuit>
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<circuit name="main">
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<a name="circuit" val="main"/>
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<a name="clabel" val=""/>
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<a name="clabelup" val="east"/>
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<a name="clabelfont" val="SansSerif plain 12"/>
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<wire from="(390,260)" to="(390,280)"/>
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<wire from="(320,240)" to="(350,240)"/>
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<wire from="(320,220)" to="(320,240)"/>
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<wire from="(280,270)" to="(350,270)"/>
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<wire from="(230,220)" to="(320,220)"/>
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<wire from="(380,260)" to="(390,260)"/>
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<wire from="(500,190)" to="(500,230)"/>
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<wire from="(480,240)" to="(500,240)"/>
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<wire from="(430,230)" to="(450,230)"/>
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<wire from="(420,240)" to="(420,320)"/>
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<wire from="(230,280)" to="(390,280)"/>
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<wire from="(270,240)" to="(270,250)"/>
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<wire from="(430,230)" to="(430,300)"/>
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<wire from="(300,190)" to="(500,190)"/>
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<wire from="(300,190)" to="(300,260)"/>
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<wire from="(230,340)" to="(500,340)"/>
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<wire from="(280,260)" to="(280,270)"/>
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<wire from="(230,260)" to="(280,260)"/>
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<wire from="(480,230)" to="(500,230)"/>
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<wire from="(230,320)" to="(420,320)"/>
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<wire from="(420,240)" to="(450,240)"/>
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<wire from="(380,250)" to="(450,250)"/>
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<wire from="(300,260)" to="(350,260)"/>
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<wire from="(500,240)" to="(500,340)"/>
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<wire from="(270,250)" to="(350,250)"/>
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<wire from="(230,300)" to="(430,300)"/>
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<wire from="(230,240)" to="(270,240)"/>
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<comp loc="(480,230)" name="Reciver"/>
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<comp lib="0" loc="(230,260)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="Trans"/>
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</comp>
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<comp lib="0" loc="(230,240)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="SPload"/>
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</comp>
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<comp lib="0" loc="(230,340)" name="Pin">
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="label" val="RPout"/>
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</comp>
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<comp lib="0" loc="(230,280)" name="Pin">
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="label" val="SPout"/>
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</comp>
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<comp loc="(380,250)" name="Sender"/>
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<comp lib="0" loc="(230,320)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="RPload"/>
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</comp>
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<comp lib="0" loc="(230,220)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="SPin"/>
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</comp>
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<comp lib="0" loc="(230,300)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="RPin"/>
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</comp>
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</circuit>
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<circuit name="Reciver">
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<a name="circuit" val="Reciver"/>
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<a name="clabel" val=""/>
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<a name="clabelup" val="east"/>
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||||
<a name="clabelfont" val="SansSerif plain 12"/>
|
||||
<wire from="(810,70)" to="(810,590)"/>
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<wire from="(560,450)" to="(770,450)"/>
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||||
<wire from="(270,50)" to="(430,50)"/>
|
||||
<wire from="(510,100)" to="(580,100)"/>
|
||||
<wire from="(390,150)" to="(410,150)"/>
|
||||
<wire from="(90,390)" to="(120,390)"/>
|
||||
<wire from="(270,370)" to="(270,380)"/>
|
||||
<wire from="(240,320)" to="(260,320)"/>
|
||||
<wire from="(600,180)" to="(630,180)"/>
|
||||
<wire from="(360,170)" to="(390,170)"/>
|
||||
<wire from="(380,100)" to="(380,110)"/>
|
||||
<wire from="(390,150)" to="(390,170)"/>
|
||||
<wire from="(770,450)" to="(770,530)"/>
|
||||
<wire from="(390,260)" to="(470,260)"/>
|
||||
<wire from="(90,370)" to="(130,370)"/>
|
||||
<wire from="(320,70)" to="(370,70)"/>
|
||||
<wire from="(580,180)" to="(600,180)"/>
|
||||
<wire from="(150,230)" to="(220,230)"/>
|
||||
<wire from="(350,90)" to="(350,130)"/>
|
||||
<wire from="(240,260)" to="(240,320)"/>
|
||||
<wire from="(290,590)" to="(810,590)"/>
|
||||
<wire from="(470,70)" to="(470,180)"/>
|
||||
<wire from="(470,70)" to="(810,70)"/>
|
||||
<wire from="(220,300)" to="(270,300)"/>
|
||||
<wire from="(280,620)" to="(730,620)"/>
|
||||
<wire from="(180,260)" to="(200,260)"/>
|
||||
<wire from="(290,550)" to="(290,590)"/>
|
||||
<wire from="(200,520)" to="(280,520)"/>
|
||||
<wire from="(410,70)" to="(420,70)"/>
|
||||
<wire from="(270,300)" to="(270,310)"/>
|
||||
<wire from="(220,230)" to="(220,300)"/>
|
||||
<wire from="(260,140)" to="(260,170)"/>
|
||||
<wire from="(560,190)" to="(560,450)"/>
|
||||
<wire from="(90,390)" to="(90,410)"/>
|
||||
<wire from="(180,290)" to="(180,390)"/>
|
||||
<wire from="(200,170)" to="(200,260)"/>
|
||||
<wire from="(400,100)" to="(410,100)"/>
|
||||
<wire from="(420,70)" to="(470,70)"/>
|
||||
<wire from="(370,230)" to="(420,230)"/>
|
||||
<wire from="(410,130)" to="(550,130)"/>
|
||||
<wire from="(430,450)" to="(560,450)"/>
|
||||
<wire from="(710,530)" to="(730,530)"/>
|
||||
<wire from="(270,50)" to="(270,120)"/>
|
||||
<wire from="(120,210)" to="(130,210)"/>
|
||||
<wire from="(580,100)" to="(580,120)"/>
|
||||
<wire from="(120,330)" to="(140,330)"/>
|
||||
<wire from="(240,340)" to="(240,450)"/>
|
||||
<wire from="(420,70)" to="(420,110)"/>
|
||||
<wire from="(240,260)" to="(370,260)"/>
|
||||
<wire from="(240,450)" to="(430,450)"/>
|
||||
<wire from="(160,290)" to="(180,290)"/>
|
||||
<wire from="(120,230)" to="(150,230)"/>
|
||||
<wire from="(730,530)" to="(730,620)"/>
|
||||
<wire from="(280,540)" to="(280,620)"/>
|
||||
<wire from="(420,110)" to="(420,230)"/>
|
||||
<wire from="(350,90)" to="(370,90)"/>
|
||||
<wire from="(120,280)" to="(130,280)"/>
|
||||
<wire from="(400,110)" to="(420,110)"/>
|
||||
<wire from="(450,280)" to="(450,380)"/>
|
||||
<wire from="(120,250)" to="(130,250)"/>
|
||||
<wire from="(240,340)" to="(260,340)"/>
|
||||
<wire from="(200,330)" to="(200,520)"/>
|
||||
<wire from="(200,330)" to="(260,330)"/>
|
||||
<wire from="(90,410)" to="(120,410)"/>
|
||||
<wire from="(470,180)" to="(550,180)"/>
|
||||
<wire from="(90,370)" to="(90,390)"/>
|
||||
<wire from="(410,100)" to="(410,130)"/>
|
||||
<wire from="(410,130)" to="(410,150)"/>
|
||||
<wire from="(570,210)" to="(600,210)"/>
|
||||
<wire from="(320,70)" to="(320,170)"/>
|
||||
<wire from="(350,350)" to="(390,350)"/>
|
||||
<wire from="(130,210)" to="(270,210)"/>
|
||||
<wire from="(130,280)" to="(130,370)"/>
|
||||
<wire from="(270,380)" to="(450,380)"/>
|
||||
<wire from="(580,140)" to="(630,140)"/>
|
||||
<wire from="(200,260)" to="(200,330)"/>
|
||||
<wire from="(370,230)" to="(370,260)"/>
|
||||
<wire from="(140,270)" to="(150,270)"/>
|
||||
<wire from="(200,170)" to="(260,170)"/>
|
||||
<wire from="(160,390)" to="(180,390)"/>
|
||||
<wire from="(430,50)" to="(430,450)"/>
|
||||
<wire from="(300,130)" to="(350,130)"/>
|
||||
<wire from="(160,280)" to="(160,290)"/>
|
||||
<wire from="(310,530)" to="(370,530)"/>
|
||||
<wire from="(140,270)" to="(140,330)"/>
|
||||
<wire from="(630,140)" to="(630,180)"/>
|
||||
<wire from="(600,180)" to="(600,210)"/>
|
||||
<wire from="(130,250)" to="(150,250)"/>
|
||||
<wire from="(390,260)" to="(390,350)"/>
|
||||
<wire from="(570,190)" to="(570,210)"/>
|
||||
<wire from="(270,210)" to="(270,290)"/>
|
||||
<wire from="(730,530)" to="(770,530)"/>
|
||||
<wire from="(450,280)" to="(470,280)"/>
|
||||
<comp lib="5" loc="(510,100)" name="Button"/>
|
||||
<comp lib="1" loc="(300,130)" name="AND Gate">
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
<a name="negate1" val="true"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(130,250)" name="Pull Resistor"/>
|
||||
<comp lib="0" loc="(360,170)" name="Pull Resistor"/>
|
||||
<comp lib="0" loc="(470,280)" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="width" val="8"/>
|
||||
<a name="label" val="Pout"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(380,110)" name="Controlled Buffer">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="control" val="left"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(580,170)" name="Counter">
|
||||
<a name="width" val="4"/>
|
||||
<a name="max" val="0x7"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(390,120)" name="NOT Gate">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(160,390)" name="T Flip-Flop"/>
|
||||
<comp lib="0" loc="(130,210)" name="Pull Resistor"/>
|
||||
<comp lib="2" loc="(310,530)" name="Multiplexer">
|
||||
<a name="disabled" val="0"/>
|
||||
<a name="enable" val="false"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(120,330)" name="Button"/>
|
||||
<comp lib="2" loc="(180,260)" name="Multiplexer">
|
||||
<a name="disabled" val="0"/>
|
||||
<a name="enable" val="false"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(150,230)" name="Pull Resistor"/>
|
||||
<comp lib="0" loc="(120,250)" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="Sin"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(410,70)" name="D Flip-Flop"/>
|
||||
<comp lib="0" loc="(370,540)" name="Clock"/>
|
||||
<comp lib="1" loc="(550,130)" name="OR Gate">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(270,290)" name="Splitter">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="fanout" val="8"/>
|
||||
<a name="incoming" val="8"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(370,530)" name="Shift Register">
|
||||
<a name="length" val="32"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(470,260)" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="label" val="Sout"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(320,170)" name="NOT Gate"/>
|
||||
<comp lib="5" loc="(120,280)" name="Button">
|
||||
<a name="label" val="Toggle"/>
|
||||
<a name="labelloc" val="west"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(120,210)" name="Pin">
|
||||
<a name="width" val="8"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="Pin"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(270,370)" name="Splitter">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="fanout" val="8"/>
|
||||
<a name="incoming" val="8"/>
|
||||
<a name="appear" val="right"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(120,230)" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="Pload"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(260,330)" name="Shift Register"/>
|
||||
<comp lib="0" loc="(290,170)" name="Clock"/>
|
||||
</circuit>
|
||||
</project>
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 25 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 20 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 24 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 24 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 35 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 38 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 42 KiB |
Binary file not shown.
|
Before Width: | Height: | Size: 74 KiB |
@ -10,53 +10,53 @@ ins_table["jmp"]=5
|
||||
ins_table["jmpz"]=6
|
||||
ins_table["jmpnz"]=7
|
||||
ins_table["imm"]=8
|
||||
mem_loc = 0
|
||||
label_table = {}
|
||||
var_table = {}
|
||||
while not stop
|
||||
print "Input file:"
|
||||
input_file = gets.chomp
|
||||
if input_file != "exit"
|
||||
output_file = input_file.gsub(".asm",".code")
|
||||
output_file = File.open(output_file, "w")
|
||||
output_file.puts("v2.0 raw")
|
||||
input_file = File.open(input_file, "r")
|
||||
input_file.each_line do |line|
|
||||
pos = line.index(":")
|
||||
if pos == nil
|
||||
mem_loc +=1
|
||||
else
|
||||
line = line.split(":")
|
||||
line = line[0]
|
||||
temp = String(mem_loc)
|
||||
while temp.length < 4
|
||||
temp = "0" + temp
|
||||
end
|
||||
label_table[line] = temp
|
||||
puts "Label "+line+" assigned "+temp
|
||||
end
|
||||
end
|
||||
input_file.rewind
|
||||
input_file.each_line do |line|
|
||||
if line.index(":") == nil
|
||||
line = line.split(" ")
|
||||
print "ins:" + line[0] + " "
|
||||
puts "arg:" + line[1]
|
||||
ins = ins_table[line[0]]
|
||||
puts "ins code:" + String(ins)
|
||||
ins = String(ins)
|
||||
arg = String(line[1])
|
||||
if label_table.has_key?(arg)
|
||||
arg = label_table[arg]
|
||||
end
|
||||
ins = arg.prepend(ins)
|
||||
puts "final ins:" + ins
|
||||
output_file.puts(ins)
|
||||
end
|
||||
end
|
||||
output_file.close
|
||||
input_file.close
|
||||
else
|
||||
stop = true
|
||||
end
|
||||
mem_loc = 0
|
||||
print "Input file:"
|
||||
input_file = gets.chomp
|
||||
if input_file != "exit"
|
||||
output_file = input_file.gsub(".asm",".code")
|
||||
output_file = File.open(output_file, "w")
|
||||
output_file.puts("v2.0 raw")
|
||||
input_file = File.open(input_file, "r")
|
||||
input_file.each_line do |line|
|
||||
pos = line.index(":")
|
||||
if pos == nil
|
||||
mem_loc +=1
|
||||
else
|
||||
line = line.split(":")
|
||||
line = line[0]
|
||||
temp = String(mem_loc)
|
||||
while temp.length < 4
|
||||
temp = "0" + temp
|
||||
end
|
||||
label_table[line] = temp
|
||||
puts "Label "+line+" assigned "+temp
|
||||
end
|
||||
end
|
||||
input_file.rewind
|
||||
input_file.each_line do |line|
|
||||
if line.index(":") == nil
|
||||
line = line.split(" ")
|
||||
print "ins:" + line[0] + " "
|
||||
puts "arg:" + line[1]
|
||||
ins = ins_table[line[0]]
|
||||
puts "ins code:" + String(ins)
|
||||
ins = String(ins)
|
||||
arg = String(line[1])
|
||||
if label_table.has_key?(arg)
|
||||
arg = label_table[arg]
|
||||
end
|
||||
ins = arg.prepend(ins)
|
||||
puts "final ins:" + ins
|
||||
output_file.puts(ins)
|
||||
end
|
||||
end
|
||||
output_file.close
|
||||
input_file.close
|
||||
else
|
||||
stop = true
|
||||
end
|
||||
end
|
||||
File diff suppressed because it is too large
Load Diff
5
comp(old)/inc.asm
Normal file
5
comp(old)/inc.asm
Normal file
@ -0,0 +1,5 @@
|
||||
ld 0001
|
||||
main:
|
||||
add 0000
|
||||
str 0000
|
||||
jmp main
|
||||
5
comp(old)/inc.code
Normal file
5
comp(old)/inc.code
Normal file
@ -0,0 +1,5 @@
|
||||
v2.0 raw
|
||||
10001
|
||||
30000
|
||||
20000
|
||||
50001
|
||||
194
comp(old)/inc.data
Normal file
194
comp(old)/inc.data
Normal file
@ -0,0 +1,194 @@
|
||||
=>,
|
||||
=>, 1=>,
|
||||
=>,
|
||||
=>, 1=>,
|
||||
1=>,
|
||||
1=>, 1=>,
|
||||
1=>,
|
||||
1=>, 1=>,
|
||||
1=>,
|
||||
1=>, 1=>,
|
||||
2=>,
|
||||
2=>, 1=>,
|
||||
2=>,
|
||||
2=>, 1=>,
|
||||
2=>,
|
||||
2=>, 1=>,
|
||||
4=>,
|
||||
4=>, 1=>,
|
||||
4=>,
|
||||
4=>, 1=>,
|
||||
4=>,
|
||||
4=>, 1=>,
|
||||
8=>,
|
||||
8=>, 1=>,
|
||||
8=>,
|
||||
8=>, 1=>,
|
||||
8=>,
|
||||
8=>, 1=>,
|
||||
16=>,
|
||||
16=>, 1=>,
|
||||
16=>,
|
||||
16=>, 1=>,
|
||||
16=>,
|
||||
16=>, 1=>,
|
||||
32=>,
|
||||
32=>, 1=>,
|
||||
32=>,
|
||||
32=>, 1=>,
|
||||
32=>,
|
||||
32=>, 1=>,
|
||||
64=>,
|
||||
64=>, 1=>,
|
||||
64=>,
|
||||
64=>, 1=>,
|
||||
64=>,
|
||||
64=>, 1=>,
|
||||
128=>,
|
||||
128=>, 1=>,
|
||||
128=>,
|
||||
128=>, 1=>,
|
||||
128=>,
|
||||
128=>, 1=>,
|
||||
256=>,
|
||||
256=>, 1=>,
|
||||
256=>,
|
||||
256=>, 1=>,
|
||||
256=>,
|
||||
256=>, 1=>,
|
||||
512=>,
|
||||
512=>, 1=>,
|
||||
512=>,
|
||||
512=>, 1=>,
|
||||
512=>,
|
||||
512=>, 1=>,
|
||||
1024=>,
|
||||
1024=>, 1=>,
|
||||
1024=>,
|
||||
1024=>, 1=>,
|
||||
1024=>,
|
||||
1024=>, 1=>,
|
||||
2048=>,
|
||||
2048=>, 1=>,
|
||||
2048=>,
|
||||
2048=>, 1=>,
|
||||
2048=>,
|
||||
2048=>, 1=>,
|
||||
4096=>,
|
||||
4096=>, 1=>,
|
||||
4096=>,
|
||||
4096=>, 1=>,
|
||||
4096=>,
|
||||
4096=>, 1=>,
|
||||
8192=>,
|
||||
8192=>, 1=>,
|
||||
8192=>,
|
||||
8192=>, 1=>,
|
||||
8192=>,
|
||||
8192=>, 1=>,
|
||||
16384=>,
|
||||
16384=>, 1=>,
|
||||
16384=>,
|
||||
16384=>, 1=>,
|
||||
16384=>,
|
||||
16384=>, 1=>,
|
||||
32768=>,
|
||||
32768=>, 1=>,
|
||||
32768=>,
|
||||
32768=>, 1=>,
|
||||
32768=>,
|
||||
32768=>, 1=>,
|
||||
65536=>,
|
||||
65536=>, 1=>,
|
||||
65536=>,
|
||||
65536=>, 1=>,
|
||||
65536=>,
|
||||
65536=>, 1=>,
|
||||
131072=>,
|
||||
131072=>, 1=>,
|
||||
131072=>,
|
||||
131072=>, 1=>,
|
||||
131072=>,
|
||||
131072=>, 1=>,
|
||||
262144=>,
|
||||
262144=>, 1=>,
|
||||
262144=>,
|
||||
262144=>, 1=>,
|
||||
262144=>,
|
||||
262144=>, 1=>,
|
||||
524288=>,
|
||||
524288=>, 1=>,
|
||||
524288=>,
|
||||
524288=>, 1=>,
|
||||
524288=>,
|
||||
524288=>, 1=>,
|
||||
1048576=>,
|
||||
1048576=>, 1=>,
|
||||
1048576=>,
|
||||
1048576=>, 1=>,
|
||||
1048576=>,
|
||||
1048576=>, 1=>,
|
||||
2097152=>,
|
||||
2097152=>, 1=>,
|
||||
2097152=>,
|
||||
2097152=>, 1=>,
|
||||
2097152=>,
|
||||
2097152=>, 1=>,
|
||||
4194304=>,
|
||||
4194304=>, 1=>,
|
||||
4194304=>,
|
||||
4194304=>, 1=>,
|
||||
4194304=>,
|
||||
4194304=>, 1=>,
|
||||
8388608=>,
|
||||
8388608=>, 1=>,
|
||||
8388608=>,
|
||||
8388608=>, 1=>,
|
||||
8388608=>,
|
||||
8388608=>, 1=>,
|
||||
16777216=>,
|
||||
16777216=>, 1=>,
|
||||
16777216=>,
|
||||
16777216=>, 1=>,
|
||||
16777216=>,
|
||||
16777216=>, 1=>,
|
||||
33554432=>,
|
||||
33554432=>, 1=>,
|
||||
33554432=>,
|
||||
33554432=>, 1=>,
|
||||
33554432=>,
|
||||
33554432=>, 1=>,
|
||||
67108864=>,
|
||||
67108864=>, 1=>,
|
||||
67108864=>,
|
||||
67108864=>, 1=>,
|
||||
67108864=>,
|
||||
67108864=>, 1=>,
|
||||
134217728=>,
|
||||
134217728=>, 1=>,
|
||||
134217728=>,
|
||||
134217728=>, 1=>,
|
||||
134217728=>,
|
||||
134217728=>, 1=>,
|
||||
268435456=>,
|
||||
268435456=>, 1=>,
|
||||
268435456=>,
|
||||
268435456=>, 1=>,
|
||||
268435456=>,
|
||||
268435456=>, 1=>,
|
||||
536870912=>,
|
||||
536870912=>, 1=>,
|
||||
536870912=>,
|
||||
536870912=>, 1=>,
|
||||
536870912=>,
|
||||
536870912=>, 1=>,
|
||||
1073741824=>,
|
||||
1073741824=>, 1=>,
|
||||
1073741824=>,
|
||||
1073741824=>, 1=>,
|
||||
1073741824=>,
|
||||
1073741824=>, 1=>,
|
||||
2147483648=>,
|
||||
2147483648=>, 1=>,
|
||||
2147483648=>,
|
||||
2147483648=>, 1=>,
|
||||
142
comp(old)/sim.rb
142
comp(old)/sim.rb
@ -12,7 +12,22 @@ n = 1
|
||||
a = 0
|
||||
zero=false
|
||||
incn = true
|
||||
mem = {}
|
||||
mem = []
|
||||
stop = false
|
||||
while !stop
|
||||
puts "Stop?"
|
||||
stop = gets.chomp
|
||||
if stop == "Y" or "y"
|
||||
stop = true
|
||||
else
|
||||
stop = false
|
||||
end
|
||||
puts "Addr:"
|
||||
addr = gets.chomp.to_i
|
||||
puts "Data:"
|
||||
data = gets.chomp.to_i
|
||||
mem[addr] = data
|
||||
end
|
||||
ins_table["1"]="ld"
|
||||
ins_table["2"]="str"
|
||||
ins_table["3"]="add"
|
||||
@ -26,66 +41,67 @@ input_file = gets.chomp
|
||||
output_file = input_file.gsub(".code",".data")
|
||||
output_file = File.open(output_file,"w")
|
||||
while n <= File.foreach(input_file).count
|
||||
line = IO.readlines(input_file)[n]
|
||||
ins = ins_table[line[0]]
|
||||
arg = String(line[1]) + String(line[2]) + String(line[3]) + String(line[4])
|
||||
arg = arg.convert_base(16,10)
|
||||
arg = Integer(arg)
|
||||
if ins == "ld"
|
||||
if arg < 65536
|
||||
if mem[arg] != nil
|
||||
a = mem[arg]
|
||||
else
|
||||
a = 0
|
||||
end
|
||||
end
|
||||
elsif ins == "str"
|
||||
if arg < 65536
|
||||
mem[arg] = a
|
||||
end
|
||||
elsif ins == "add"
|
||||
if mem[arg] != nil
|
||||
if mem[arg] + a < 4294967296
|
||||
a = mem[arg] + a
|
||||
if a == 0
|
||||
z=true
|
||||
end
|
||||
else
|
||||
exit
|
||||
end
|
||||
end
|
||||
elsif ins == "sub"
|
||||
if mem[arg] != nil
|
||||
if a - mem[arg] >= 0
|
||||
a = mem[arg] + a
|
||||
else
|
||||
exit
|
||||
end
|
||||
end
|
||||
elsif ins == "jmp"
|
||||
n = arg + 1
|
||||
incn = false
|
||||
elsif ins == "jmpz"
|
||||
if zero
|
||||
n = arg + 1
|
||||
incn = false
|
||||
end
|
||||
elsif ins == "jmpnz"
|
||||
if not zero
|
||||
n = arg + 1
|
||||
incn = false
|
||||
end
|
||||
elsif ins == "imm"
|
||||
a = arg
|
||||
end
|
||||
if incn
|
||||
n += 1
|
||||
else
|
||||
incn = true
|
||||
end
|
||||
string = ""
|
||||
mem.each do |key, value|
|
||||
string += "#{key}=>#{value}, "
|
||||
output_file.puts string
|
||||
end
|
||||
puts "Executing"
|
||||
line = IO.readlines(input_file)[n]
|
||||
ins = ins_table[line[0]]
|
||||
arg = String(line[1]) + String(line[2]) + String(line[3]) + String(line[4])
|
||||
arg = arg.convert_base(16,10)
|
||||
arg = Integer(arg)
|
||||
if ins == "ld"
|
||||
if arg < 65536
|
||||
if mem[arg] != nil
|
||||
a = mem[arg]
|
||||
else
|
||||
a = 0
|
||||
end
|
||||
end
|
||||
elsif ins == "str"
|
||||
if arg < 65536
|
||||
mem[arg] = a
|
||||
end
|
||||
elsif ins == "add"
|
||||
if mem[arg] != nil
|
||||
if mem[arg] + a < 4294967296
|
||||
a = mem[arg] + a
|
||||
if a == 0
|
||||
z=true
|
||||
end
|
||||
else
|
||||
exit
|
||||
end
|
||||
end
|
||||
elsif ins == "sub"
|
||||
if mem[arg] != nil
|
||||
if a - mem[arg] >= 0
|
||||
a = mem[arg] + a
|
||||
else
|
||||
exit
|
||||
end
|
||||
end
|
||||
elsif ins == "jmp"
|
||||
n = arg + 1
|
||||
incn = false
|
||||
elsif ins == "jmpz"
|
||||
if zero
|
||||
n = arg + 1
|
||||
incn = false
|
||||
end
|
||||
elsif ins == "jmpnz"
|
||||
if not zero
|
||||
n = arg + 1
|
||||
incn = false
|
||||
end
|
||||
elsif ins == "imm"
|
||||
a = arg
|
||||
end
|
||||
if incn
|
||||
n += 1
|
||||
else
|
||||
incn = true
|
||||
end
|
||||
string = ""
|
||||
mem.each do |key, value|
|
||||
string += "#{key}=>#{value}, "
|
||||
output_file.puts string
|
||||
end
|
||||
end
|
||||
|
||||
3
multicycle cpu/..code
Normal file
3
multicycle cpu/..code
Normal file
@ -0,0 +1,3 @@
|
||||
v2.0 raw
|
||||
03
|
||||
09
|
||||
3
multicycle cpu/.code
Normal file
3
multicycle cpu/.code
Normal file
@ -0,0 +1,3 @@
|
||||
v2.0 raw
|
||||
03
|
||||
09
|
||||
@ -11,8 +11,8 @@ if len(sys.argv) == 2:
|
||||
else:
|
||||
SOURCE_FILENAME = raw_input('input file:')
|
||||
t = SOURCE_FILENAME.strip( '.asm' )
|
||||
OUTPUT_FILENAME = t+ ".code"
|
||||
|
||||
OUTPUT_FILENAME = raw_input("output file:")
|
||||
print(OUTPUT_FILENAME)
|
||||
VALID_LABEL = re.compile("[a-zA-Z_][a-zA-Z0-9_]*")
|
||||
|
||||
#key is lowercase instruction name
|
||||
@ -82,9 +82,11 @@ for line in asm_lines:
|
||||
#check for a definition
|
||||
if len(tokens) > 0 and tokens[0] == ".def":
|
||||
if len(tokens) >= 3:
|
||||
(name, value) = tokens[1:]
|
||||
(name, value) = tokens[1:]
|
||||
|
||||
assert_label(name)
|
||||
labels[name] = convert_number(value)
|
||||
labels[name] = convert_number(value)
|
||||
|
||||
#remove the three tokens in the .def statement
|
||||
tokens = tokens[3:]
|
||||
else:
|
||||
|
||||
@ -78,8 +78,8 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
</options>
|
||||
<mappings>
|
||||
<tool lib="6" map="Button2" name="Menu Tool"/>
|
||||
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
|
||||
<tool lib="6" map="Button3" name="Menu Tool"/>
|
||||
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
|
||||
</mappings>
|
||||
<toolbar>
|
||||
<tool lib="6" name="Poke Tool"/>
|
||||
@ -130,44 +130,22 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
</appear>
|
||||
<wire from="(430,150)" to="(430,170)"/>
|
||||
<wire from="(510,380)" to="(510,390)"/>
|
||||
<wire from="(270,310)" to="(310,310)"/>
|
||||
<wire from="(430,490)" to="(430,590)"/>
|
||||
<wire from="(570,250)" to="(570,260)"/>
|
||||
<wire from="(300,160)" to="(300,170)"/>
|
||||
<wire from="(510,360)" to="(550,360)"/>
|
||||
<wire from="(410,180)" to="(410,200)"/>
|
||||
<wire from="(460,400)" to="(460,410)"/>
|
||||
<wire from="(300,450)" to="(340,450)"/>
|
||||
<wire from="(280,410)" to="(460,410)"/>
|
||||
<wire from="(700,240)" to="(700,260)"/>
|
||||
<wire from="(270,360)" to="(270,500)"/>
|
||||
<wire from="(390,150)" to="(390,200)"/>
|
||||
<wire from="(530,340)" to="(820,340)"/>
|
||||
<wire from="(510,340)" to="(510,360)"/>
|
||||
<wire from="(570,260)" to="(570,280)"/>
|
||||
<wire from="(360,230)" to="(360,350)"/>
|
||||
<wire from="(220,380)" to="(300,380)"/>
|
||||
<wire from="(310,230)" to="(340,230)"/>
|
||||
<wire from="(320,200)" to="(390,200)"/>
|
||||
<wire from="(720,280)" to="(770,280)"/>
|
||||
<wire from="(300,170)" to="(300,190)"/>
|
||||
<wire from="(340,220)" to="(520,220)"/>
|
||||
<wire from="(480,180)" to="(520,180)"/>
|
||||
<wire from="(700,300)" to="(750,300)"/>
|
||||
<wire from="(680,270)" to="(680,290)"/>
|
||||
<wire from="(500,410)" to="(580,410)"/>
|
||||
<wire from="(310,230)" to="(310,300)"/>
|
||||
<wire from="(240,450)" to="(240,470)"/>
|
||||
<wire from="(530,310)" to="(530,340)"/>
|
||||
<wire from="(220,170)" to="(220,230)"/>
|
||||
<wire from="(270,310)" to="(310,310)"/>
|
||||
<wire from="(480,450)" to="(550,450)"/>
|
||||
<wire from="(430,490)" to="(430,590)"/>
|
||||
<wire from="(750,240)" to="(790,240)"/>
|
||||
<wire from="(570,250)" to="(570,260)"/>
|
||||
<wire from="(430,210)" to="(480,210)"/>
|
||||
<wire from="(220,260)" to="(570,260)"/>
|
||||
<wire from="(300,160)" to="(300,170)"/>
|
||||
<wire from="(390,150)" to="(430,150)"/>
|
||||
<wire from="(510,360)" to="(550,360)"/>
|
||||
<wire from="(660,240)" to="(660,290)"/>
|
||||
<wire from="(360,350)" to="(410,350)"/>
|
||||
<wire from="(790,240)" to="(790,250)"/>
|
||||
<wire from="(410,180)" to="(410,200)"/>
|
||||
<wire from="(220,170)" to="(300,170)"/>
|
||||
<wire from="(380,300)" to="(380,400)"/>
|
||||
<wire from="(790,290)" to="(790,610)"/>
|
||||
@ -176,56 +154,74 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
<wire from="(500,410)" to="(500,530)"/>
|
||||
<wire from="(440,350)" to="(460,350)"/>
|
||||
<wire from="(270,360)" to="(410,360)"/>
|
||||
<wire from="(660,240)" to="(700,240)"/>
|
||||
<wire from="(460,400)" to="(460,410)"/>
|
||||
<wire from="(300,450)" to="(340,450)"/>
|
||||
<wire from="(280,410)" to="(460,410)"/>
|
||||
<wire from="(700,240)" to="(700,260)"/>
|
||||
<wire from="(280,610)" to="(790,610)"/>
|
||||
<wire from="(660,240)" to="(700,240)"/>
|
||||
<wire from="(750,240)" to="(750,300)"/>
|
||||
<wire from="(390,530)" to="(500,530)"/>
|
||||
<wire from="(270,360)" to="(270,500)"/>
|
||||
<wire from="(280,410)" to="(280,610)"/>
|
||||
<wire from="(460,370)" to="(460,380)"/>
|
||||
<wire from="(500,390)" to="(510,390)"/>
|
||||
<wire from="(240,470)" to="(340,470)"/>
|
||||
<wire from="(220,260)" to="(220,310)"/>
|
||||
<wire from="(390,150)" to="(390,200)"/>
|
||||
<wire from="(360,230)" to="(540,230)"/>
|
||||
<wire from="(540,200)" to="(540,230)"/>
|
||||
<wire from="(530,340)" to="(820,340)"/>
|
||||
<wire from="(510,340)" to="(510,360)"/>
|
||||
<wire from="(570,260)" to="(570,280)"/>
|
||||
<wire from="(360,230)" to="(360,350)"/>
|
||||
<wire from="(340,220)" to="(340,230)"/>
|
||||
<wire from="(220,380)" to="(300,380)"/>
|
||||
<wire from="(460,310)" to="(460,330)"/>
|
||||
<wire from="(390,490)" to="(390,530)"/>
|
||||
<wire from="(170,570)" to="(370,570)"/>
|
||||
<wire from="(310,230)" to="(340,230)"/>
|
||||
<wire from="(370,490)" to="(370,570)"/>
|
||||
<wire from="(320,200)" to="(390,200)"/>
|
||||
<wire from="(300,380)" to="(300,450)"/>
|
||||
<wire from="(720,280)" to="(770,280)"/>
|
||||
<wire from="(580,370)" to="(580,410)"/>
|
||||
<wire from="(300,170)" to="(300,190)"/>
|
||||
<wire from="(270,310)" to="(270,360)"/>
|
||||
<wire from="(340,220)" to="(520,220)"/>
|
||||
<wire from="(460,310)" to="(530,310)"/>
|
||||
<wire from="(480,180)" to="(520,180)"/>
|
||||
<wire from="(700,300)" to="(750,300)"/>
|
||||
<wire from="(500,340)" to="(510,340)"/>
|
||||
<wire from="(340,180)" to="(410,180)"/>
|
||||
<wire from="(450,190)" to="(500,190)"/>
|
||||
<wire from="(340,300)" to="(380,300)"/>
|
||||
<wire from="(820,270)" to="(820,340)"/>
|
||||
<wire from="(810,270)" to="(820,270)"/>
|
||||
<wire from="(440,370)" to="(440,400)"/>
|
||||
<wire from="(500,190)" to="(500,210)"/>
|
||||
<wire from="(680,270)" to="(680,290)"/>
|
||||
<wire from="(440,370)" to="(460,370)"/>
|
||||
<wire from="(610,270)" to="(680,270)"/>
|
||||
<wire from="(500,190)" to="(500,210)"/>
|
||||
<wire from="(440,370)" to="(440,400)"/>
|
||||
<wire from="(480,180)" to="(480,210)"/>
|
||||
<wire from="(380,400)" to="(440,400)"/>
|
||||
<wire from="(610,270)" to="(680,270)"/>
|
||||
<wire from="(500,410)" to="(580,410)"/>
|
||||
<wire from="(510,380)" to="(550,380)"/>
|
||||
<wire from="(380,400)" to="(440,400)"/>
|
||||
<wire from="(310,230)" to="(310,300)"/>
|
||||
<wire from="(770,260)" to="(770,280)"/>
|
||||
<wire from="(590,290)" to="(660,290)"/>
|
||||
<wire from="(220,450)" to="(240,450)"/>
|
||||
<comp lib="4" loc="(440,350)" name="Register">
|
||||
<a name="width" val="32"/>
|
||||
<wire from="(240,450)" to="(240,470)"/>
|
||||
<comp lib="0" loc="(410,490)" name="Clock">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(340,180)" name="Multiplier">
|
||||
<a name="width" val="32"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(500,390)" name="Comparator">
|
||||
<a name="width" val="32"/>
|
||||
<a name="mode" val="unsigned"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(610,270)" name="Multiplier">
|
||||
<comp lib="3" loc="(810,270)" name="Multiplier">
|
||||
<a name="width" val="32"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(340,300)" name="Register">
|
||||
<comp lib="3" loc="(720,280)" name="Multiplier">
|
||||
<a name="width" val="32"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(170,570)" name="Pin">
|
||||
@ -237,14 +233,23 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="in"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(500,340)" name="Comparator">
|
||||
<comp lib="0" loc="(220,230)" name="Pin">
|
||||
<a name="width" val="32"/>
|
||||
<a name="mode" val="unsigned"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="new pass"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(720,280)" name="Multiplier">
|
||||
<comp lib="4" loc="(480,450)" name="RAM">
|
||||
<a name="addrWidth" val="24"/>
|
||||
<a name="dataWidth" val="32"/>
|
||||
<a name="bus" val="separate"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(320,320)" name="Clock">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(440,350)" name="Register">
|
||||
<a name="width" val="32"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(810,270)" name="Multiplier">
|
||||
<comp lib="3" loc="(540,200)" name="Multiplier">
|
||||
<a name="width" val="32"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(550,450)" name="Pin">
|
||||
@ -254,52 +259,47 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
<a name="label" val="out"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(540,200)" name="Multiplier">
|
||||
<comp lib="3" loc="(450,190)" name="Multiplier">
|
||||
<a name="width" val="32"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(500,340)" name="Comparator">
|
||||
<a name="width" val="32"/>
|
||||
<a name="mode" val="unsigned"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(610,270)" name="Multiplier">
|
||||
<a name="width" val="32"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(220,500)" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="set"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(580,370)" name="AND Gate">
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(500,390)" name="Comparator">
|
||||
<a name="width" val="32"/>
|
||||
<a name="mode" val="unsigned"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(340,300)" name="Register">
|
||||
<a name="width" val="32"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(420,370)" name="Clock">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(220,310)" name="Pin">
|
||||
<a name="width" val="32"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="user pass"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(170,590)" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="load"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(420,370)" name="Clock">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(320,320)" name="Clock">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(410,490)" name="Clock">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(480,450)" name="RAM">
|
||||
<a name="addrWidth" val="24"/>
|
||||
<a name="dataWidth" val="32"/>
|
||||
<a name="bus" val="separate"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(220,380)" name="Pin">
|
||||
<a name="width" val="24"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="loc"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(220,230)" name="Pin">
|
||||
<a name="width" val="32"/>
|
||||
<comp lib="0" loc="(170,590)" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="new pass"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(220,500)" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="set"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(450,190)" name="Multiplier">
|
||||
<a name="width" val="32"/>
|
||||
<a name="label" val="load"/>
|
||||
</comp>
|
||||
</circuit>
|
||||
<circuit name="main">
|
||||
@ -312,8 +312,8 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
<wire from="(400,430)" to="(400,460)"/>
|
||||
<wire from="(240,410)" to="(260,410)"/>
|
||||
<wire from="(290,400)" to="(290,540)"/>
|
||||
<wire from="(270,390)" to="(270,580)"/>
|
||||
<wire from="(350,410)" to="(350,560)"/>
|
||||
<wire from="(270,390)" to="(270,580)"/>
|
||||
<wire from="(260,560)" to="(260,680)"/>
|
||||
<wire from="(270,610)" to="(270,730)"/>
|
||||
<wire from="(450,400)" to="(470,400)"/>
|
||||
@ -336,21 +336,10 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
<wire from="(240,680)" to="(260,680)"/>
|
||||
<wire from="(270,390)" to="(400,390)"/>
|
||||
<wire from="(280,660)" to="(280,740)"/>
|
||||
<comp lib="0" loc="(240,610)" name="Pin">
|
||||
<a name="width" val="24"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="loc"/>
|
||||
</comp>
|
||||
<comp loc="(610,390)" name="a-track">
|
||||
<a name="label" val="Peter"/>
|
||||
</comp>
|
||||
<comp loc="(610,470)" name="a-track">
|
||||
<a name="label" val="Charlie"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(240,540)" name="Pin">
|
||||
<comp lib="0" loc="(240,460)" name="Pin">
|
||||
<a name="width" val="32"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="user pass"/>
|
||||
<a name="label" val="new pass"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(240,780)" name="Pin">
|
||||
<a name="output" val="true"/>
|
||||
@ -361,20 +350,25 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||
<a name="label" val="set"/>
|
||||
<a name="labelloc" val="west"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(240,460)" name="Pin">
|
||||
<a name="width" val="32"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="new pass"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(440,440)" name="NOT Gate"/>
|
||||
<comp lib="5" loc="(240,730)" name="Button">
|
||||
<a name="label" val="store"/>
|
||||
<a name="labelloc" val="west"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(240,610)" name="Pin">
|
||||
<a name="width" val="24"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="loc"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(240,680)" name="Pin">
|
||||
<a name="width" val="32"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="in"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(240,540)" name="Pin">
|
||||
<a name="width" val="32"/>
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="user pass"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(440,440)" name="NOT Gate"/>
|
||||
</circuit>
|
||||
</project>
|
||||
|
||||
Loading…
Reference in New Issue
Block a user