diff --git a/ASync Serial.circ b/ASync Serial.circ
new file mode 100644
index 0000000..4dc309d
--- /dev/null
+++ b/ASync Serial.circ
@@ -0,0 +1,501 @@
+
+
+This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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+ addr/data: 8 8
+0
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diff --git a/PLG1.circ b/PLG1/PLG1.circ
similarity index 100%
rename from PLG1.circ
rename to PLG1/PLG1.circ
diff --git a/RAM files/gates b/PLG1/gates
similarity index 100%
rename from RAM files/gates
rename to PLG1/gates
diff --git a/TK16/images/images/ALU.png b/TK16/images/images/ALU.png
deleted file mode 100644
index 88166f9..0000000
Binary files a/TK16/images/images/ALU.png and /dev/null differ
diff --git a/TK16/images/images/Jump Control.png b/TK16/images/images/Jump Control.png
deleted file mode 100644
index 3f1fc14..0000000
Binary files a/TK16/images/images/Jump Control.png and /dev/null differ
diff --git a/TK16/images/images/Key and Display.png b/TK16/images/images/Key and Display.png
deleted file mode 100644
index f5a5106..0000000
Binary files a/TK16/images/images/Key and Display.png and /dev/null differ
diff --git a/TK16/images/images/LoadStore.png b/TK16/images/images/LoadStore.png
deleted file mode 100644
index 45b6ffd..0000000
Binary files a/TK16/images/images/LoadStore.png and /dev/null differ
diff --git a/TK16/images/images/Stack.png b/TK16/images/images/Stack.png
deleted file mode 100644
index a9b91d5..0000000
Binary files a/TK16/images/images/Stack.png and /dev/null differ
diff --git a/TK16/images/images/ins dec.png b/TK16/images/images/ins dec.png
deleted file mode 100644
index 009a821..0000000
Binary files a/TK16/images/images/ins dec.png and /dev/null differ
diff --git a/TK16/images/images/main.png b/TK16/images/images/main.png
deleted file mode 100644
index d0feee4..0000000
Binary files a/TK16/images/images/main.png and /dev/null differ
diff --git a/TK16/images/images/q238.png b/TK16/images/images/q238.png
deleted file mode 100644
index 668b536..0000000
Binary files a/TK16/images/images/q238.png and /dev/null differ
diff --git a/comp(old)/asm.rb b/comp(old)/asm.rb
index fe0aa7b..b3e7c3b 100644
--- a/comp(old)/asm.rb
+++ b/comp(old)/asm.rb
@@ -10,53 +10,53 @@ ins_table["jmp"]=5
ins_table["jmpz"]=6
ins_table["jmpnz"]=7
ins_table["imm"]=8
-mem_loc = 0
label_table = {}
var_table = {}
while not stop
-print "Input file:"
-input_file = gets.chomp
-if input_file != "exit"
-output_file = input_file.gsub(".asm",".code")
-output_file = File.open(output_file, "w")
-output_file.puts("v2.0 raw")
-input_file = File.open(input_file, "r")
-input_file.each_line do |line|
-pos = line.index(":")
-if pos == nil
-mem_loc +=1
-else
-line = line.split(":")
-line = line[0]
-temp = String(mem_loc)
-while temp.length < 4
-temp = "0" + temp
-end
-label_table[line] = temp
-puts "Label "+line+" assigned "+temp
-end
-end
-input_file.rewind
-input_file.each_line do |line|
-if line.index(":") == nil
-line = line.split(" ")
-print "ins:" + line[0] + " "
-puts "arg:" + line[1]
-ins = ins_table[line[0]]
-puts "ins code:" + String(ins)
-ins = String(ins)
-arg = String(line[1])
-if label_table.has_key?(arg)
-arg = label_table[arg]
-end
-ins = arg.prepend(ins)
-puts "final ins:" + ins
-output_file.puts(ins)
-end
-end
-output_file.close
-input_file.close
-else
-stop = true
-end
+ mem_loc = 0
+ print "Input file:"
+ input_file = gets.chomp
+ if input_file != "exit"
+ output_file = input_file.gsub(".asm",".code")
+ output_file = File.open(output_file, "w")
+ output_file.puts("v2.0 raw")
+ input_file = File.open(input_file, "r")
+ input_file.each_line do |line|
+ pos = line.index(":")
+ if pos == nil
+ mem_loc +=1
+ else
+ line = line.split(":")
+ line = line[0]
+ temp = String(mem_loc)
+ while temp.length < 4
+ temp = "0" + temp
+ end
+ label_table[line] = temp
+ puts "Label "+line+" assigned "+temp
+ end
+ end
+ input_file.rewind
+ input_file.each_line do |line|
+ if line.index(":") == nil
+ line = line.split(" ")
+ print "ins:" + line[0] + " "
+ puts "arg:" + line[1]
+ ins = ins_table[line[0]]
+ puts "ins code:" + String(ins)
+ ins = String(ins)
+ arg = String(line[1])
+ if label_table.has_key?(arg)
+ arg = label_table[arg]
+ end
+ ins = arg.prepend(ins)
+ puts "final ins:" + ins
+ output_file.puts(ins)
+ end
+ end
+ output_file.close
+ input_file.close
+ else
+ stop = true
+ end
end
\ No newline at end of file
diff --git a/comp(old)/comp.circ b/comp(old)/comp.circ
index 52eb9c1..c1d8838 100644
--- a/comp(old)/comp.circ
+++ b/comp(old)/comp.circ
@@ -106,8 +106,8 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
+
@@ -141,7 +141,8 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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@@ -153,14 +154,13 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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@@ -174,25 +174,25 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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@@ -208,6 +208,7 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
+
@@ -242,6 +243,7 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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@@ -249,52 +251,6 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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@@ -303,9 +259,68 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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@@ -313,54 +328,44 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
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@@ -375,44 +380,48 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
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-
@@ -420,6 +429,7 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
+
@@ -432,51 +442,54 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
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@@ -489,14 +502,13 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
+
-
-
@@ -508,13 +520,13 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
+
+
-
-
@@ -531,39 +543,48 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
+
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@@ -573,125 +594,229 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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@@ -700,6 +825,43 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
+
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@@ -708,65 +870,31 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
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@@ -775,123 +903,12 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
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diff --git a/comp(old)/inc.asm b/comp(old)/inc.asm
new file mode 100644
index 0000000..441ccbf
--- /dev/null
+++ b/comp(old)/inc.asm
@@ -0,0 +1,5 @@
+ld 0001
+main:
+add 0000
+str 0000
+jmp main
\ No newline at end of file
diff --git a/comp(old)/inc.code b/comp(old)/inc.code
new file mode 100644
index 0000000..c09931f
--- /dev/null
+++ b/comp(old)/inc.code
@@ -0,0 +1,5 @@
+v2.0 raw
+10001
+30000
+20000
+50001
diff --git a/comp(old)/inc.data b/comp(old)/inc.data
new file mode 100644
index 0000000..ce1d136
--- /dev/null
+++ b/comp(old)/inc.data
@@ -0,0 +1,194 @@
+=>,
+=>, 1=>,
+=>,
+=>, 1=>,
+1=>,
+1=>, 1=>,
+1=>,
+1=>, 1=>,
+1=>,
+1=>, 1=>,
+2=>,
+2=>, 1=>,
+2=>,
+2=>, 1=>,
+2=>,
+2=>, 1=>,
+4=>,
+4=>, 1=>,
+4=>,
+4=>, 1=>,
+4=>,
+4=>, 1=>,
+8=>,
+8=>, 1=>,
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+8=>, 1=>,
+16=>,
+16=>, 1=>,
+16=>,
+16=>, 1=>,
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+32=>,
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+32=>, 1=>,
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+64=>, 1=>,
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+64=>, 1=>,
+128=>,
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+2147483648=>,
+2147483648=>, 1=>,
diff --git a/comp(old)/sim.rb b/comp(old)/sim.rb
index 399ceaa..f02ccd2 100644
--- a/comp(old)/sim.rb
+++ b/comp(old)/sim.rb
@@ -12,7 +12,22 @@ n = 1
a = 0
zero=false
incn = true
-mem = {}
+mem = []
+stop = false
+while !stop
+puts "Stop?"
+stop = gets.chomp
+if stop == "Y" or "y"
+stop = true
+else
+stop = false
+end
+puts "Addr:"
+addr = gets.chomp.to_i
+puts "Data:"
+data = gets.chomp.to_i
+mem[addr] = data
+end
ins_table["1"]="ld"
ins_table["2"]="str"
ins_table["3"]="add"
@@ -26,66 +41,67 @@ input_file = gets.chomp
output_file = input_file.gsub(".code",".data")
output_file = File.open(output_file,"w")
while n <= File.foreach(input_file).count
-line = IO.readlines(input_file)[n]
-ins = ins_table[line[0]]
-arg = String(line[1]) + String(line[2]) + String(line[3]) + String(line[4])
-arg = arg.convert_base(16,10)
-arg = Integer(arg)
-if ins == "ld"
-if arg < 65536
-if mem[arg] != nil
-a = mem[arg]
-else
-a = 0
-end
-end
-elsif ins == "str"
-if arg < 65536
-mem[arg] = a
-end
-elsif ins == "add"
-if mem[arg] != nil
-if mem[arg] + a < 4294967296
-a = mem[arg] + a
-if a == 0
-z=true
-end
-else
-exit
-end
-end
-elsif ins == "sub"
-if mem[arg] != nil
-if a - mem[arg] >= 0
-a = mem[arg] + a
-else
-exit
-end
-end
-elsif ins == "jmp"
-n = arg + 1
-incn = false
-elsif ins == "jmpz"
-if zero
-n = arg + 1
-incn = false
-end
-elsif ins == "jmpnz"
-if not zero
-n = arg + 1
-incn = false
-end
-elsif ins == "imm"
-a = arg
-end
-if incn
-n += 1
-else
-incn = true
-end
-string = ""
-mem.each do |key, value|
-string += "#{key}=>#{value}, "
-output_file.puts string
-end
+ puts "Executing"
+ line = IO.readlines(input_file)[n]
+ ins = ins_table[line[0]]
+ arg = String(line[1]) + String(line[2]) + String(line[3]) + String(line[4])
+ arg = arg.convert_base(16,10)
+ arg = Integer(arg)
+ if ins == "ld"
+ if arg < 65536
+ if mem[arg] != nil
+ a = mem[arg]
+ else
+ a = 0
+ end
+ end
+ elsif ins == "str"
+ if arg < 65536
+ mem[arg] = a
+ end
+ elsif ins == "add"
+ if mem[arg] != nil
+ if mem[arg] + a < 4294967296
+ a = mem[arg] + a
+ if a == 0
+ z=true
+ end
+ else
+ exit
+ end
+ end
+ elsif ins == "sub"
+ if mem[arg] != nil
+ if a - mem[arg] >= 0
+ a = mem[arg] + a
+ else
+ exit
+ end
+ end
+ elsif ins == "jmp"
+ n = arg + 1
+ incn = false
+ elsif ins == "jmpz"
+ if zero
+ n = arg + 1
+ incn = false
+ end
+ elsif ins == "jmpnz"
+ if not zero
+ n = arg + 1
+ incn = false
+ end
+ elsif ins == "imm"
+ a = arg
+ end
+ if incn
+ n += 1
+ else
+ incn = true
+ end
+ string = ""
+ mem.each do |key, value|
+ string += "#{key}=>#{value}, "
+ output_file.puts string
+ end
end
diff --git a/multicycle cpu/..code b/multicycle cpu/..code
new file mode 100644
index 0000000..67af788
--- /dev/null
+++ b/multicycle cpu/..code
@@ -0,0 +1,3 @@
+v2.0 raw
+03
+09
diff --git a/multicycle cpu/.code b/multicycle cpu/.code
new file mode 100644
index 0000000..67af788
--- /dev/null
+++ b/multicycle cpu/.code
@@ -0,0 +1,3 @@
+v2.0 raw
+03
+09
diff --git a/multicycle cpu/assembler.py b/multicycle cpu/assembler.py
index 676ea83..2c90ac7 100644
--- a/multicycle cpu/assembler.py
+++ b/multicycle cpu/assembler.py
@@ -11,8 +11,8 @@ if len(sys.argv) == 2:
else:
SOURCE_FILENAME = raw_input('input file:')
t = SOURCE_FILENAME.strip( '.asm' )
-OUTPUT_FILENAME = t+ ".code"
-
+OUTPUT_FILENAME = raw_input("output file:")
+print(OUTPUT_FILENAME)
VALID_LABEL = re.compile("[a-zA-Z_][a-zA-Z0-9_]*")
#key is lowercase instruction name
@@ -82,9 +82,11 @@ for line in asm_lines:
#check for a definition
if len(tokens) > 0 and tokens[0] == ".def":
if len(tokens) >= 3:
- (name, value) = tokens[1:]
+ (name, value) = tokens[1:]
+
assert_label(name)
- labels[name] = convert_number(value)
+ labels[name] = convert_number(value)
+
#remove the three tokens in the .def statement
tokens = tokens[3:]
else:
diff --git a/TK16/assembler/.asm.code b/multicycle cpu/inc.code
similarity index 100%
rename from TK16/assembler/.asm.code
rename to multicycle cpu/inc.code
diff --git a/pass protected ram.circ b/pass protected ram.circ
index 04b4d2d..12c6440 100644
--- a/pass protected ram.circ
+++ b/pass protected ram.circ
@@ -78,8 +78,8 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
+
@@ -130,44 +130,22 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
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@@ -176,56 +154,74 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
+
+
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@@ -237,14 +233,23 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
+
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+
@@ -254,52 +259,47 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
+
+
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@@ -312,8 +312,8 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
+
@@ -336,21 +336,10 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
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@@ -361,20 +350,25 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
-
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