257 lines
14 KiB
SQL
257 lines
14 KiB
SQL
{ RLC_R, REG_B, INV, INV, 8, TYPE_NONE, "rlc b" }, // 00
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{ RLC_R, REG_C, INV, INV, 8, TYPE_NONE, "rlc c" }, // 01
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{ RLC_R, REG_D, INV, INV, 8, TYPE_NONE, "rlc d" }, // 02
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{ RLC_R, REG_E, INV, INV, 8, TYPE_NONE, "rlc e" }, // 03
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{ RLC_R, REG_H, INV, INV, 8, TYPE_NONE, "rlc h" }, // 04
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{ RLC_R, REG_L, INV, INV, 8, TYPE_NONE, "rlc l" }, // 05
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{ RLC_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "rlc (hl)" }, // 06
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{ RLC_R, REG_A, INV, INV, 8, TYPE_NONE, "rlc a" }, // 07
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{ RRC_R, REG_B, INV, INV, 8, TYPE_NONE, "rrc b" }, // 08
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{ RRC_R, REG_C, INV, INV, 8, TYPE_NONE, "rrc c" }, // 09
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{ RRC_R, REG_D, INV, INV, 8, TYPE_NONE, "rrc d" }, // 0a
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{ RRC_R, REG_E, INV, INV, 8, TYPE_NONE, "rrc e" }, // 0b
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{ RRC_R, REG_H, INV, INV, 8, TYPE_NONE, "rrc h" }, // 0c
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{ RRC_R, REG_L, INV, INV, 8, TYPE_NONE, "rrc l" }, // 0d
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{ RRC_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "rrc (hl)" }, // 0e
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{ RRC_R, REG_A, INV, INV, 8, TYPE_NONE, "rrc a" }, // 0f
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{ RL_R, REG_B, INV, INV, 8, TYPE_NONE, "rl b" }, // 10
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{ RL_R, REG_C, INV, INV, 8, TYPE_NONE, "rl c" }, // 11
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{ RL_R, REG_D, INV, INV, 8, TYPE_NONE, "rl d" }, // 12
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{ RL_R, REG_E, INV, INV, 8, TYPE_NONE, "rl e" }, // 13
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{ RL_R, REG_H, INV, INV, 8, TYPE_NONE, "rl h" }, // 14
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{ RL_R, REG_L, INV, INV, 8, TYPE_NONE, "rl l" }, // 15
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{ RL_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "rl (hl)" }, // 16
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{ RL_R, REG_A, INV, INV, 8, TYPE_NONE, "rl a" }, // 17
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{ RR_R, REG_B, INV, INV, 8, TYPE_NONE, "rr b" }, // 18
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{ RR_R, REG_C, INV, INV, 8, TYPE_NONE, "rr c" }, // 19
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{ RR_R, REG_D, INV, INV, 8, TYPE_NONE, "rr d" }, // 1a
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{ RR_R, REG_E, INV, INV, 8, TYPE_NONE, "rr e" }, // 1b
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{ RR_R, REG_H, INV, INV, 8, TYPE_NONE, "rr h" }, // 1c
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{ RR_R, REG_L, INV, INV, 8, TYPE_NONE, "rr l" }, // 1d
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{ RR_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "rr (hl)" }, // 1e
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{ RR_R, REG_A, INV, INV, 8, TYPE_NONE, "rr a" }, // 1f
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{ SLA_R, REG_B, INV, INV, 8, TYPE_NONE, "sla b" }, // 20
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{ SLA_R, REG_C, INV, INV, 8, TYPE_NONE, "sla c" }, // 21
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{ SLA_R, REG_D, INV, INV, 8, TYPE_NONE, "sla d" }, // 22
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{ SLA_R, REG_E, INV, INV, 8, TYPE_NONE, "sla e" }, // 23
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{ SLA_R, REG_H, INV, INV, 8, TYPE_NONE, "sla h" }, // 24
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{ SLA_R, REG_L, INV, INV, 8, TYPE_NONE, "sla l" }, // 25
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{ SLA_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "sla (hl)" }, // 26
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{ SLA_R, REG_A, INV, INV, 8, TYPE_NONE, "sla a" }, // 27
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{ SRA_R, REG_B, INV, INV, 8, TYPE_NONE, "sra b" }, // 28
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{ SRA_R, REG_C, INV, INV, 8, TYPE_NONE, "sra c" }, // 29
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{ SRA_R, REG_D, INV, INV, 8, TYPE_NONE, "sra d" }, // 2a
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{ SRA_R, REG_E, INV, INV, 8, TYPE_NONE, "sra e" }, // 2b
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{ SRA_R, REG_H, INV, INV, 8, TYPE_NONE, "sra h" }, // 2c
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{ SRA_R, REG_L, INV, INV, 8, TYPE_NONE, "sra l" }, // 2d
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{ SRA_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "sra (hl)" }, // 2e
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{ SRA_R, REG_A, INV, INV, 8, TYPE_NONE, "sra a" }, // 2f
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{ SLL_R, REG_B, INV, INV, 8, TYPE_NONE, "sll b" }, // 30
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{ SLL_R, REG_C, INV, INV, 8, TYPE_NONE, "sll c" }, // 31
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{ SLL_R, REG_D, INV, INV, 8, TYPE_NONE, "sll d" }, // 32
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{ SLL_R, REG_E, INV, INV, 8, TYPE_NONE, "sll e" }, // 33
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{ SLL_R, REG_H, INV, INV, 8, TYPE_NONE, "sll h" }, // 34
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{ SLL_R, REG_L, INV, INV, 8, TYPE_NONE, "sll l" }, // 35
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{ SLL_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "sll (hl)" }, // 36
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{ SLL_R, REG_A, INV, INV, 8, TYPE_NONE, "sll a" }, // 37
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{ SRL_R, REG_B, INV, INV, 8, TYPE_NONE, "srl b" }, // 38
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{ SRL_R, REG_C, INV, INV, 8, TYPE_NONE, "srl c" }, // 39
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{ SRL_R, REG_D, INV, INV, 8, TYPE_NONE, "srl d" }, // 3a
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{ SRL_R, REG_E, INV, INV, 8, TYPE_NONE, "srl e" }, // 3b
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{ SRL_R, REG_H, INV, INV, 8, TYPE_NONE, "srl h" }, // 3c
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{ SRL_R, REG_L, INV, INV, 8, TYPE_NONE, "srl l" }, // 3d
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{ SRL_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "srl (hl)" }, // 3e
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{ SRL_R, REG_A, INV, INV, 8, TYPE_NONE, "srl a" }, // 3f
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{ BIT_R, 0, REG_B, INV, 8, TYPE_NONE, "bit 0,b" }, // 40
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{ BIT_R, 0, REG_C, INV, 8, TYPE_NONE, "bit 0,c" }, // 41
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{ BIT_R, 0, REG_D, INV, 8, TYPE_NONE, "bit 0,d" }, // 42
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{ BIT_R, 0, REG_E, INV, 8, TYPE_NONE, "bit 0,e" }, // 43
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{ BIT_R, 0, REG_H, INV, 8, TYPE_NONE, "bit 0,h" }, // 44
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{ BIT_R, 0, REG_L, INV, 8, TYPE_NONE, "bit 0,l" }, // 45
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{ BIT_MRR, 0, REG_HL, INV, 12, TYPE_NONE, "bit 0,(hl)" }, // 46
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{ BIT_R, 0, REG_A, INV, 8, TYPE_NONE, "bit 0,a" }, // 47
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{ BIT_R, 1, REG_B, INV, 8, TYPE_NONE, "bit 1,b" }, // 48
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{ BIT_R, 1, REG_C, INV, 8, TYPE_NONE, "bit 1,c" }, // 49
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{ BIT_R, 1, REG_D, INV, 8, TYPE_NONE, "bit 1,d" }, // 4a
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{ BIT_R, 1, REG_E, INV, 8, TYPE_NONE, "bit 1,e" }, // 4b
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{ BIT_R, 1, REG_H, INV, 8, TYPE_NONE, "bit 1,h" }, // 4c
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{ BIT_R, 1, REG_L, INV, 8, TYPE_NONE, "bit 1,l" }, // 4d
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{ BIT_MRR, 1, REG_HL, INV, 12, TYPE_NONE, "bit 1,(hl)" }, // 4e
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{ BIT_R, 1, REG_A, INV, 8, TYPE_NONE, "bit 1,a" }, // 4f
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{ BIT_R, 2, REG_B, INV, 8, TYPE_NONE, "bit 2,b" }, // 50
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{ BIT_R, 2, REG_C, INV, 8, TYPE_NONE, "bit 2,c" }, // 51
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{ BIT_R, 2, REG_D, INV, 8, TYPE_NONE, "bit 2,d" }, // 52
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{ BIT_R, 2, REG_E, INV, 8, TYPE_NONE, "bit 2,e" }, // 53
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{ BIT_R, 2, REG_H, INV, 8, TYPE_NONE, "bit 2,h" }, // 54
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{ BIT_R, 2, REG_L, INV, 8, TYPE_NONE, "bit 2,l" }, // 55
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{ BIT_MRR, 2, REG_HL, INV, 12, TYPE_NONE, "bit 2,(hl)" }, // 56
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{ BIT_R, 2, REG_A, INV, 8, TYPE_NONE, "bit 2,a" }, // 57
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{ BIT_R, 3, REG_B, INV, 8, TYPE_NONE, "bit 3,b" }, // 58
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{ BIT_R, 3, REG_C, INV, 8, TYPE_NONE, "bit 3,c" }, // 59
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{ BIT_R, 3, REG_D, INV, 8, TYPE_NONE, "bit 3,d" }, // 5a
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{ BIT_R, 3, REG_E, INV, 8, TYPE_NONE, "bit 3,e" }, // 5b
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{ BIT_R, 3, REG_H, INV, 8, TYPE_NONE, "bit 3,h" }, // 5c
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{ BIT_R, 3, REG_L, INV, 8, TYPE_NONE, "bit 3,l" }, // 5d
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{ BIT_MRR, 3, REG_HL, INV, 12, TYPE_NONE, "bit 3,(hl)" }, // 5e
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{ BIT_R, 3, REG_A, INV, 8, TYPE_NONE, "bit 3,a" }, // 5f
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{ BIT_R, 4, REG_B, INV, 8, TYPE_NONE, "bit 4,b" }, // 60
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{ BIT_R, 4, REG_C, INV, 8, TYPE_NONE, "bit 4,c" }, // 61
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{ BIT_R, 4, REG_D, INV, 8, TYPE_NONE, "bit 4,d" }, // 62
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{ BIT_R, 4, REG_E, INV, 8, TYPE_NONE, "bit 4,e" }, // 63
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{ BIT_R, 4, REG_H, INV, 8, TYPE_NONE, "bit 4,h" }, // 64
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{ BIT_R, 4, REG_L, INV, 8, TYPE_NONE, "bit 4,l" }, // 65
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{ BIT_MRR, 4, REG_HL, INV, 12, TYPE_NONE, "bit 4,(hl)" }, // 66
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{ BIT_R, 4, REG_A, INV, 8, TYPE_NONE, "bit 4,a" }, // 67
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{ BIT_R, 5, REG_B, INV, 8, TYPE_NONE, "bit 5,b" }, // 68
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{ BIT_R, 5, REG_C, INV, 8, TYPE_NONE, "bit 5,c" }, // 69
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{ BIT_R, 5, REG_D, INV, 8, TYPE_NONE, "bit 5,d" }, // 6a
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{ BIT_R, 5, REG_E, INV, 8, TYPE_NONE, "bit 5,e" }, // 6b
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{ BIT_R, 5, REG_H, INV, 8, TYPE_NONE, "bit 5,h" }, // 6c
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{ BIT_R, 5, REG_L, INV, 8, TYPE_NONE, "bit 5,l" }, // 6d
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{ BIT_MRR, 5, REG_HL, INV, 12, TYPE_NONE, "bit 5,(hl)" }, // 6e
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{ BIT_R, 5, REG_A, INV, 8, TYPE_NONE, "bit 5,a" }, // 6f
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{ BIT_R, 6, REG_B, INV, 8, TYPE_NONE, "bit 6,b" }, // 70
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{ BIT_R, 6, REG_C, INV, 8, TYPE_NONE, "bit 6,c" }, // 71
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{ BIT_R, 6, REG_D, INV, 8, TYPE_NONE, "bit 6,d" }, // 72
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{ BIT_R, 6, REG_E, INV, 8, TYPE_NONE, "bit 6,e" }, // 73
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{ BIT_R, 6, REG_H, INV, 8, TYPE_NONE, "bit 6,h" }, // 74
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{ BIT_R, 6, REG_L, INV, 8, TYPE_NONE, "bit 6,l" }, // 75
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{ BIT_MRR, 6, REG_HL, INV, 12, TYPE_NONE, "bit 6,(hl)" }, // 76
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{ BIT_R, 6, REG_A, INV, 8, TYPE_NONE, "bit 6,a" }, // 77
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{ BIT_R, 7, REG_B, INV, 8, TYPE_NONE, "bit 7,b" }, // 78
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{ BIT_R, 7, REG_C, INV, 8, TYPE_NONE, "bit 7,c" }, // 79
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{ BIT_R, 7, REG_D, INV, 8, TYPE_NONE, "bit 7,d" }, // 7a
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{ BIT_R, 7, REG_E, INV, 8, TYPE_NONE, "bit 7,e" }, // 7b
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{ BIT_R, 7, REG_H, INV, 8, TYPE_NONE, "bit 7,h" }, // 7c
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{ BIT_R, 7, REG_L, INV, 8, TYPE_NONE, "bit 7,l" }, // 7d
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{ BIT_MRR, 7, REG_HL, INV, 12, TYPE_NONE, "bit 7,(hl)" }, // 7e
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{ BIT_R, 7, REG_A, INV, 8, TYPE_NONE, "bit 7,a" }, // 7f
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{ RES_R, 0, REG_B, INV, 8, TYPE_NONE, "res 0,b" }, // 80
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{ RES_R, 0, REG_C, INV, 8, TYPE_NONE, "res 0,c" }, // 81
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{ RES_R, 0, REG_D, INV, 8, TYPE_NONE, "res 0,d" }, // 82
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{ RES_R, 0, REG_E, INV, 8, TYPE_NONE, "res 0,e" }, // 83
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{ RES_R, 0, REG_H, INV, 8, TYPE_NONE, "res 0,h" }, // 84
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{ RES_R, 0, REG_L, INV, 8, TYPE_NONE, "res 0,l" }, // 85
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{ RES_MRR, 0, REG_HL, INV, 15, TYPE_NONE, "res 0,(hl)" }, // 86
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{ RES_R, 0, REG_A, INV, 8, TYPE_NONE, "res 0,a" }, // 87
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{ RES_R, 1, REG_B, INV, 8, TYPE_NONE, "res 1,b" }, // 88
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{ RES_R, 1, REG_C, INV, 8, TYPE_NONE, "res 1,c" }, // 89
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{ RES_R, 1, REG_D, INV, 8, TYPE_NONE, "res 1,d" }, // 8a
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{ RES_R, 1, REG_E, INV, 8, TYPE_NONE, "res 1,e" }, // 8b
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{ RES_R, 1, REG_H, INV, 8, TYPE_NONE, "res 1,h" }, // 8c
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{ RES_R, 1, REG_L, INV, 8, TYPE_NONE, "res 1,l" }, // 8d
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{ RES_MRR, 1, REG_HL, INV, 15, TYPE_NONE, "res 1,(hl)" }, // 8e
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{ RES_R, 1, REG_A, INV, 8, TYPE_NONE, "res 1,a" }, // 8f
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{ RES_R, 2, REG_B, INV, 8, TYPE_NONE, "res 2,b" }, // 90
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{ RES_R, 2, REG_C, INV, 8, TYPE_NONE, "res 2,c" }, // 91
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{ RES_R, 2, REG_D, INV, 8, TYPE_NONE, "res 2,d" }, // 92
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{ RES_R, 2, REG_E, INV, 8, TYPE_NONE, "res 2,e" }, // 93
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{ RES_R, 2, REG_H, INV, 8, TYPE_NONE, "res 2,h" }, // 94
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{ RES_R, 2, REG_L, INV, 8, TYPE_NONE, "res 2,l" }, // 95
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{ RES_MRR, 2, REG_HL, INV, 15, TYPE_NONE, "res 2,(hl)" }, // 96
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{ RES_R, 2, REG_A, INV, 8, TYPE_NONE, "res 2,a" }, // 97
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{ RES_R, 3, REG_B, INV, 8, TYPE_NONE, "res 3,b" }, // 98
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{ RES_R, 3, REG_C, INV, 8, TYPE_NONE, "res 3,c" }, // 99
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{ RES_R, 3, REG_D, INV, 8, TYPE_NONE, "res 3,d" }, // 9a
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{ RES_R, 3, REG_E, INV, 8, TYPE_NONE, "res 3,e" }, // 9b
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{ RES_R, 3, REG_H, INV, 8, TYPE_NONE, "res 3,h" }, // 9c
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{ RES_R, 3, REG_L, INV, 8, TYPE_NONE, "res 3,l" }, // 9d
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{ RES_MRR, 3, REG_HL, INV, 15, TYPE_NONE, "res 3,(hl)" }, // 9e
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{ RES_R, 3, REG_A, INV, 8, TYPE_NONE, "res 3,a" }, // 9f
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{ RES_R, 4, REG_B, INV, 8, TYPE_NONE, "res 4,b" }, // a0
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{ RES_R, 4, REG_C, INV, 8, TYPE_NONE, "res 4,c" }, // a1
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{ RES_R, 4, REG_D, INV, 8, TYPE_NONE, "res 4,d" }, // a2
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{ RES_R, 4, REG_E, INV, 8, TYPE_NONE, "res 4,e" }, // a3
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{ RES_R, 4, REG_H, INV, 8, TYPE_NONE, "res 4,h" }, // a4
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{ RES_R, 4, REG_L, INV, 8, TYPE_NONE, "res 4,l" }, // a5
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{ RES_MRR, 4, REG_HL, INV, 15, TYPE_NONE, "res 4,(hl)" }, // a6
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{ RES_R, 4, REG_A, INV, 8, TYPE_NONE, "res 4,a" }, // a7
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{ RES_R, 5, REG_B, INV, 8, TYPE_NONE, "res 5,b" }, // a8
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{ RES_R, 5, REG_C, INV, 8, TYPE_NONE, "res 5,c" }, // a9
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{ RES_R, 5, REG_D, INV, 8, TYPE_NONE, "res 5,d" }, // aa
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{ RES_R, 5, REG_E, INV, 8, TYPE_NONE, "res 5,e" }, // ab
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{ RES_R, 5, REG_H, INV, 8, TYPE_NONE, "res 5,h" }, // ac
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{ RES_R, 5, REG_L, INV, 8, TYPE_NONE, "res 5,l" }, // ad
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{ RES_MRR, 5, REG_HL, INV, 15, TYPE_NONE, "res 5,(hl)" }, // ae
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{ RES_R, 5, REG_A, INV, 8, TYPE_NONE, "res 5,a" }, // af
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{ RES_R, 6, REG_B, INV, 8, TYPE_NONE, "res 6,b" }, // b0
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{ RES_R, 6, REG_C, INV, 8, TYPE_NONE, "res 6,c" }, // b1
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{ RES_R, 6, REG_D, INV, 8, TYPE_NONE, "res 6,d" }, // b2
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{ RES_R, 6, REG_E, INV, 8, TYPE_NONE, "res 6,e" }, // b3
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{ RES_R, 6, REG_H, INV, 8, TYPE_NONE, "res 6,h" }, // b4
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{ RES_R, 6, REG_L, INV, 8, TYPE_NONE, "res 6,l" }, // b5
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{ RES_MRR, 6, REG_HL, INV, 15, TYPE_NONE, "res 6,(hl)" }, // b6
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{ RES_R, 6, REG_A, INV, 8, TYPE_NONE, "res 6,a" }, // b7
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{ RES_R, 7, REG_B, INV, 8, TYPE_NONE, "res 7,b" }, // b8
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{ RES_R, 7, REG_C, INV, 8, TYPE_NONE, "res 7,c" }, // b9
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{ RES_R, 7, REG_D, INV, 8, TYPE_NONE, "res 7,d" }, // ba
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{ RES_R, 7, REG_E, INV, 8, TYPE_NONE, "res 7,e" }, // bb
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{ RES_R, 7, REG_H, INV, 8, TYPE_NONE, "res 7,h" }, // bc
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{ RES_R, 7, REG_L, INV, 8, TYPE_NONE, "res 7,l" }, // bd
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{ RES_MRR, 7, REG_HL, INV, 15, TYPE_NONE, "res 7,(hl)" }, // be
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{ RES_R, 7, REG_A, INV, 8, TYPE_NONE, "res 7,a" }, // bf
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{ SET_R, 0, REG_B, INV, 8, TYPE_NONE, "set 0,b" }, // c0
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{ SET_R, 0, REG_C, INV, 8, TYPE_NONE, "set 0,c" }, // c1
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{ SET_R, 0, REG_D, INV, 8, TYPE_NONE, "set 0,d" }, // c2
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{ SET_R, 0, REG_E, INV, 8, TYPE_NONE, "set 0,e" }, // c3
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{ SET_R, 0, REG_H, INV, 8, TYPE_NONE, "set 0,h" }, // c4
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{ SET_R, 0, REG_L, INV, 8, TYPE_NONE, "set 0,l" }, // c5
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{ SET_MRR, 0, REG_HL, INV, 15, TYPE_NONE, "set 0,(hl)" }, // c6
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{ SET_R, 0, REG_A, INV, 8, TYPE_NONE, "set 0,a" }, // c7
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{ SET_R, 1, REG_B, INV, 8, TYPE_NONE, "set 1,b" }, // c8
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{ SET_R, 1, REG_C, INV, 8, TYPE_NONE, "set 1,c" }, // c9
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{ SET_R, 1, REG_D, INV, 8, TYPE_NONE, "set 1,d" }, // ca
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{ SET_R, 1, REG_E, INV, 8, TYPE_NONE, "set 1,e" }, // cb
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{ SET_R, 1, REG_H, INV, 8, TYPE_NONE, "set 1,h" }, // cc
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{ SET_R, 1, REG_L, INV, 8, TYPE_NONE, "set 1,l" }, // cd
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{ SET_MRR, 1, REG_HL, INV, 15, TYPE_NONE, "set 1,(hl)" }, // ce
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{ SET_R, 1, REG_A, INV, 8, TYPE_NONE, "set 1,a" }, // cf
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{ SET_R, 2, REG_B, INV, 8, TYPE_NONE, "set 2,b" }, // d0
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{ SET_R, 2, REG_C, INV, 8, TYPE_NONE, "set 2,c" }, // d1
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{ SET_R, 2, REG_D, INV, 8, TYPE_NONE, "set 2,d" }, // d2
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{ SET_R, 2, REG_E, INV, 8, TYPE_NONE, "set 2,e" }, // d3
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{ SET_R, 2, REG_H, INV, 8, TYPE_NONE, "set 2,h" }, // d4
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{ SET_R, 2, REG_L, INV, 8, TYPE_NONE, "set 2,l" }, // d5
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{ SET_MRR, 2, REG_HL, INV, 15, TYPE_NONE, "set 2,(hl)" }, // d6
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{ SET_R, 2, REG_A, INV, 8, TYPE_NONE, "set 2,a" }, // d7
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{ SET_R, 3, REG_B, INV, 8, TYPE_NONE, "set 3,b" }, // d8
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{ SET_R, 3, REG_C, INV, 8, TYPE_NONE, "set 3,c" }, // d9
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{ SET_R, 3, REG_D, INV, 8, TYPE_NONE, "set 3,d" }, // da
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{ SET_R, 3, REG_E, INV, 8, TYPE_NONE, "set 3,e" }, // db
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{ SET_R, 3, REG_H, INV, 8, TYPE_NONE, "set 3,h" }, // dc
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{ SET_R, 3, REG_L, INV, 8, TYPE_NONE, "set 3,l" }, // dd
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{ SET_MRR, 3, REG_HL, INV, 15, TYPE_NONE, "set 3,(hl)" }, // de
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{ SET_R, 3, REG_A, INV, 8, TYPE_NONE, "set 3,a" }, // df
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{ SET_R, 4, REG_B, INV, 8, TYPE_NONE, "set 4,b" }, // e0
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{ SET_R, 4, REG_C, INV, 8, TYPE_NONE, "set 4,c" }, // e1
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{ SET_R, 4, REG_D, INV, 8, TYPE_NONE, "set 4,d" }, // e2
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{ SET_R, 4, REG_E, INV, 8, TYPE_NONE, "set 4,e" }, // e3
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{ SET_R, 4, REG_H, INV, 8, TYPE_NONE, "set 4,h" }, // e4
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{ SET_R, 4, REG_L, INV, 8, TYPE_NONE, "set 4,l" }, // e5
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{ SET_MRR, 4, REG_HL, INV, 15, TYPE_NONE, "set 4,(hl)" }, // e6
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{ SET_R, 4, REG_A, INV, 8, TYPE_NONE, "set 4,a" }, // e7
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{ SET_R, 5, REG_B, INV, 8, TYPE_NONE, "set 5,b" }, // e8
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{ SET_R, 5, REG_C, INV, 8, TYPE_NONE, "set 5,c" }, // e9
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{ SET_R, 5, REG_D, INV, 8, TYPE_NONE, "set 5,d" }, // ea
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{ SET_R, 5, REG_E, INV, 8, TYPE_NONE, "set 5,e" }, // eb
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{ SET_R, 5, REG_H, INV, 8, TYPE_NONE, "set 5,h" }, // ec
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{ SET_R, 5, REG_L, INV, 8, TYPE_NONE, "set 5,l" }, // ed
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{ SET_MRR, 5, REG_HL, INV, 15, TYPE_NONE, "set 5,(hl)" }, // ee
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{ SET_R, 5, REG_A, INV, 8, TYPE_NONE, "set 5,a" }, // ef
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{ SET_R, 6, REG_B, INV, 8, TYPE_NONE, "set 6,b" }, // f0
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{ SET_R, 6, REG_C, INV, 8, TYPE_NONE, "set 6,c" }, // f1
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{ SET_R, 6, REG_D, INV, 8, TYPE_NONE, "set 6,d" }, // f2
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{ SET_R, 6, REG_E, INV, 8, TYPE_NONE, "set 6,e" }, // f3
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{ SET_R, 6, REG_H, INV, 8, TYPE_NONE, "set 6,h" }, // f4
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{ SET_R, 6, REG_L, INV, 8, TYPE_NONE, "set 6,l" }, // f5
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{ SET_MRR, 6, REG_HL, INV, 15, TYPE_NONE, "set 6,(hl)" }, // f6
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{ SET_R, 6, REG_A, INV, 8, TYPE_NONE, "set 6,a" }, // f7
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{ SET_R, 7, REG_B, INV, 8, TYPE_NONE, "set 7,b" }, // f8
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{ SET_R, 7, REG_C, INV, 8, TYPE_NONE, "set 7,c" }, // f9
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{ SET_R, 7, REG_D, INV, 8, TYPE_NONE, "set 7,d" }, // fa
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{ SET_R, 7, REG_E, INV, 8, TYPE_NONE, "set 7,e" }, // fb
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{ SET_R, 7, REG_H, INV, 8, TYPE_NONE, "set 7,h" }, // fc
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{ SET_R, 7, REG_L, INV, 8, TYPE_NONE, "set 7,l" }, // fd
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{ SET_MRR, 7, REG_HL, INV, 15, TYPE_NONE, "set 7,(hl)" }, // fe
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{ SET_R, 7, REG_A, INV, 8, TYPE_NONE, "set 7,a" }, // ff
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