{ RLC_R, REG_B, INV, INV, 8, TYPE_NONE, "rlc b" },	// 00
{ RLC_R, REG_C, INV, INV, 8, TYPE_NONE, "rlc c" },	// 01
{ RLC_R, REG_D, INV, INV, 8, TYPE_NONE, "rlc d" },	// 02
{ RLC_R, REG_E, INV, INV, 8, TYPE_NONE, "rlc e" },	// 03
{ RLC_R, REG_H, INV, INV, 8, TYPE_NONE, "rlc h" },	// 04
{ RLC_R, REG_L, INV, INV, 8, TYPE_NONE, "rlc l" },	// 05
{ RLC_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "rlc (hl)" },	// 06
{ RLC_R, REG_A, INV, INV, 8, TYPE_NONE, "rlc a" },	// 07
{ RRC_R, REG_B, INV, INV, 8, TYPE_NONE, "rrc b" },	// 08
{ RRC_R, REG_C, INV, INV, 8, TYPE_NONE, "rrc c" },	// 09
{ RRC_R, REG_D, INV, INV, 8, TYPE_NONE, "rrc d" },	// 0a
{ RRC_R, REG_E, INV, INV, 8, TYPE_NONE, "rrc e" },	// 0b
{ RRC_R, REG_H, INV, INV, 8, TYPE_NONE, "rrc h" },	// 0c
{ RRC_R, REG_L, INV, INV, 8, TYPE_NONE, "rrc l" },	// 0d
{ RRC_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "rrc (hl)" },	// 0e
{ RRC_R, REG_A, INV, INV, 8, TYPE_NONE, "rrc a" },	// 0f
{ RL_R, REG_B, INV, INV, 8, TYPE_NONE, "rl b" },	// 10
{ RL_R, REG_C, INV, INV, 8, TYPE_NONE, "rl c" },	// 11
{ RL_R, REG_D, INV, INV, 8, TYPE_NONE, "rl d" },	// 12
{ RL_R, REG_E, INV, INV, 8, TYPE_NONE, "rl e" },	// 13
{ RL_R, REG_H, INV, INV, 8, TYPE_NONE, "rl h" },	// 14
{ RL_R, REG_L, INV, INV, 8, TYPE_NONE, "rl l" },	// 15
{ RL_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "rl (hl)" },	// 16
{ RL_R, REG_A, INV, INV, 8, TYPE_NONE, "rl a" },	// 17
{ RR_R, REG_B, INV, INV, 8, TYPE_NONE, "rr b" },	// 18
{ RR_R, REG_C, INV, INV, 8, TYPE_NONE, "rr c" },	// 19
{ RR_R, REG_D, INV, INV, 8, TYPE_NONE, "rr d" },	// 1a
{ RR_R, REG_E, INV, INV, 8, TYPE_NONE, "rr e" },	// 1b
{ RR_R, REG_H, INV, INV, 8, TYPE_NONE, "rr h" },	// 1c
{ RR_R, REG_L, INV, INV, 8, TYPE_NONE, "rr l" },	// 1d
{ RR_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "rr (hl)" },	// 1e
{ RR_R, REG_A, INV, INV, 8, TYPE_NONE, "rr a" },	// 1f
{ SLA_R, REG_B, INV, INV, 8, TYPE_NONE, "sla b" },	// 20
{ SLA_R, REG_C, INV, INV, 8, TYPE_NONE, "sla c" },	// 21
{ SLA_R, REG_D, INV, INV, 8, TYPE_NONE, "sla d" },	// 22
{ SLA_R, REG_E, INV, INV, 8, TYPE_NONE, "sla e" },	// 23
{ SLA_R, REG_H, INV, INV, 8, TYPE_NONE, "sla h" },	// 24
{ SLA_R, REG_L, INV, INV, 8, TYPE_NONE, "sla l" },	// 25
{ SLA_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "sla (hl)" },	// 26
{ SLA_R, REG_A, INV, INV, 8, TYPE_NONE, "sla a" },	// 27
{ SRA_R, REG_B, INV, INV, 8, TYPE_NONE, "sra b" },	// 28
{ SRA_R, REG_C, INV, INV, 8, TYPE_NONE, "sra c" },	// 29
{ SRA_R, REG_D, INV, INV, 8, TYPE_NONE, "sra d" },	// 2a
{ SRA_R, REG_E, INV, INV, 8, TYPE_NONE, "sra e" },	// 2b
{ SRA_R, REG_H, INV, INV, 8, TYPE_NONE, "sra h" },	// 2c
{ SRA_R, REG_L, INV, INV, 8, TYPE_NONE, "sra l" },	// 2d
{ SRA_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "sra (hl)" },	// 2e
{ SRA_R, REG_A, INV, INV, 8, TYPE_NONE, "sra a" },	// 2f
{ SLL_R, REG_B, INV, INV, 8, TYPE_NONE, "sll b" },	// 30
{ SLL_R, REG_C, INV, INV, 8, TYPE_NONE, "sll c" },	// 31
{ SLL_R, REG_D, INV, INV, 8, TYPE_NONE, "sll d" },	// 32
{ SLL_R, REG_E, INV, INV, 8, TYPE_NONE, "sll e" },	// 33
{ SLL_R, REG_H, INV, INV, 8, TYPE_NONE, "sll h" },	// 34
{ SLL_R, REG_L, INV, INV, 8, TYPE_NONE, "sll l" },	// 35
{ SLL_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "sll (hl)" },	// 36
{ SLL_R, REG_A, INV, INV, 8, TYPE_NONE, "sll a" },	// 37
{ SRL_R, REG_B, INV, INV, 8, TYPE_NONE, "srl b" },	// 38
{ SRL_R, REG_C, INV, INV, 8, TYPE_NONE, "srl c" },	// 39
{ SRL_R, REG_D, INV, INV, 8, TYPE_NONE, "srl d" },	// 3a
{ SRL_R, REG_E, INV, INV, 8, TYPE_NONE, "srl e" },	// 3b
{ SRL_R, REG_H, INV, INV, 8, TYPE_NONE, "srl h" },	// 3c
{ SRL_R, REG_L, INV, INV, 8, TYPE_NONE, "srl l" },	// 3d
{ SRL_MRR, REG_HL, INV, INV, 15, TYPE_NONE, "srl (hl)" },	// 3e
{ SRL_R, REG_A, INV, INV, 8, TYPE_NONE, "srl a" },	// 3f
{ BIT_R, 0, REG_B, INV, 8, TYPE_NONE, "bit 0,b" },	// 40
{ BIT_R, 0, REG_C, INV, 8, TYPE_NONE, "bit 0,c" },	// 41
{ BIT_R, 0, REG_D, INV, 8, TYPE_NONE, "bit 0,d" },	// 42
{ BIT_R, 0, REG_E, INV, 8, TYPE_NONE, "bit 0,e" },	// 43
{ BIT_R, 0, REG_H, INV, 8, TYPE_NONE, "bit 0,h" },	// 44
{ BIT_R, 0, REG_L, INV, 8, TYPE_NONE, "bit 0,l" },	// 45
{ BIT_MRR, 0, REG_HL, INV, 12, TYPE_NONE, "bit 0,(hl)" },	// 46
{ BIT_R, 0, REG_A, INV, 8, TYPE_NONE, "bit 0,a" },	// 47
{ BIT_R, 1, REG_B, INV, 8, TYPE_NONE, "bit 1,b" },	// 48
{ BIT_R, 1, REG_C, INV, 8, TYPE_NONE, "bit 1,c" },	// 49
{ BIT_R, 1, REG_D, INV, 8, TYPE_NONE, "bit 1,d" },	// 4a
{ BIT_R, 1, REG_E, INV, 8, TYPE_NONE, "bit 1,e" },	// 4b
{ BIT_R, 1, REG_H, INV, 8, TYPE_NONE, "bit 1,h" },	// 4c
{ BIT_R, 1, REG_L, INV, 8, TYPE_NONE, "bit 1,l" },	// 4d
{ BIT_MRR, 1, REG_HL, INV, 12, TYPE_NONE, "bit 1,(hl)" },	// 4e
{ BIT_R, 1, REG_A, INV, 8, TYPE_NONE, "bit 1,a" },	// 4f
{ BIT_R, 2, REG_B, INV, 8, TYPE_NONE, "bit 2,b" },	// 50
{ BIT_R, 2, REG_C, INV, 8, TYPE_NONE, "bit 2,c" },	// 51
{ BIT_R, 2, REG_D, INV, 8, TYPE_NONE, "bit 2,d" },	// 52
{ BIT_R, 2, REG_E, INV, 8, TYPE_NONE, "bit 2,e" },	// 53
{ BIT_R, 2, REG_H, INV, 8, TYPE_NONE, "bit 2,h" },	// 54
{ BIT_R, 2, REG_L, INV, 8, TYPE_NONE, "bit 2,l" },	// 55
{ BIT_MRR, 2, REG_HL, INV, 12, TYPE_NONE, "bit 2,(hl)" },	// 56
{ BIT_R, 2, REG_A, INV, 8, TYPE_NONE, "bit 2,a" },	// 57
{ BIT_R, 3, REG_B, INV, 8, TYPE_NONE, "bit 3,b" },	// 58
{ BIT_R, 3, REG_C, INV, 8, TYPE_NONE, "bit 3,c" },	// 59
{ BIT_R, 3, REG_D, INV, 8, TYPE_NONE, "bit 3,d" },	// 5a
{ BIT_R, 3, REG_E, INV, 8, TYPE_NONE, "bit 3,e" },	// 5b
{ BIT_R, 3, REG_H, INV, 8, TYPE_NONE, "bit 3,h" },	// 5c
{ BIT_R, 3, REG_L, INV, 8, TYPE_NONE, "bit 3,l" },	// 5d
{ BIT_MRR, 3, REG_HL, INV, 12, TYPE_NONE, "bit 3,(hl)" },	// 5e
{ BIT_R, 3, REG_A, INV, 8, TYPE_NONE, "bit 3,a" },	// 5f
{ BIT_R, 4, REG_B, INV, 8, TYPE_NONE, "bit 4,b" },	// 60
{ BIT_R, 4, REG_C, INV, 8, TYPE_NONE, "bit 4,c" },	// 61
{ BIT_R, 4, REG_D, INV, 8, TYPE_NONE, "bit 4,d" },	// 62
{ BIT_R, 4, REG_E, INV, 8, TYPE_NONE, "bit 4,e" },	// 63
{ BIT_R, 4, REG_H, INV, 8, TYPE_NONE, "bit 4,h" },	// 64
{ BIT_R, 4, REG_L, INV, 8, TYPE_NONE, "bit 4,l" },	// 65
{ BIT_MRR, 4, REG_HL, INV, 12, TYPE_NONE, "bit 4,(hl)" },	// 66
{ BIT_R, 4, REG_A, INV, 8, TYPE_NONE, "bit 4,a" },	// 67
{ BIT_R, 5, REG_B, INV, 8, TYPE_NONE, "bit 5,b" },	// 68
{ BIT_R, 5, REG_C, INV, 8, TYPE_NONE, "bit 5,c" },	// 69
{ BIT_R, 5, REG_D, INV, 8, TYPE_NONE, "bit 5,d" },	// 6a
{ BIT_R, 5, REG_E, INV, 8, TYPE_NONE, "bit 5,e" },	// 6b
{ BIT_R, 5, REG_H, INV, 8, TYPE_NONE, "bit 5,h" },	// 6c
{ BIT_R, 5, REG_L, INV, 8, TYPE_NONE, "bit 5,l" },	// 6d
{ BIT_MRR, 5, REG_HL, INV, 12, TYPE_NONE, "bit 5,(hl)" },	// 6e
{ BIT_R, 5, REG_A, INV, 8, TYPE_NONE, "bit 5,a" },	// 6f
{ BIT_R, 6, REG_B, INV, 8, TYPE_NONE, "bit 6,b" },	// 70
{ BIT_R, 6, REG_C, INV, 8, TYPE_NONE, "bit 6,c" },	// 71
{ BIT_R, 6, REG_D, INV, 8, TYPE_NONE, "bit 6,d" },	// 72
{ BIT_R, 6, REG_E, INV, 8, TYPE_NONE, "bit 6,e" },	// 73
{ BIT_R, 6, REG_H, INV, 8, TYPE_NONE, "bit 6,h" },	// 74
{ BIT_R, 6, REG_L, INV, 8, TYPE_NONE, "bit 6,l" },	// 75
{ BIT_MRR, 6, REG_HL, INV, 12, TYPE_NONE, "bit 6,(hl)" },	// 76
{ BIT_R, 6, REG_A, INV, 8, TYPE_NONE, "bit 6,a" },	// 77
{ BIT_R, 7, REG_B, INV, 8, TYPE_NONE, "bit 7,b" },	// 78
{ BIT_R, 7, REG_C, INV, 8, TYPE_NONE, "bit 7,c" },	// 79
{ BIT_R, 7, REG_D, INV, 8, TYPE_NONE, "bit 7,d" },	// 7a
{ BIT_R, 7, REG_E, INV, 8, TYPE_NONE, "bit 7,e" },	// 7b
{ BIT_R, 7, REG_H, INV, 8, TYPE_NONE, "bit 7,h" },	// 7c
{ BIT_R, 7, REG_L, INV, 8, TYPE_NONE, "bit 7,l" },	// 7d
{ BIT_MRR, 7, REG_HL, INV, 12, TYPE_NONE, "bit 7,(hl)" },	// 7e
{ BIT_R, 7, REG_A, INV, 8, TYPE_NONE, "bit 7,a" },	// 7f
{ RES_R, 0, REG_B, INV, 8, TYPE_NONE, "res 0,b" },	// 80
{ RES_R, 0, REG_C, INV, 8, TYPE_NONE, "res 0,c" },	// 81
{ RES_R, 0, REG_D, INV, 8, TYPE_NONE, "res 0,d" },	// 82
{ RES_R, 0, REG_E, INV, 8, TYPE_NONE, "res 0,e" },	// 83
{ RES_R, 0, REG_H, INV, 8, TYPE_NONE, "res 0,h" },	// 84
{ RES_R, 0, REG_L, INV, 8, TYPE_NONE, "res 0,l" },	// 85
{ RES_MRR, 0, REG_HL, INV, 15, TYPE_NONE, "res 0,(hl)" },	// 86
{ RES_R, 0, REG_A, INV, 8, TYPE_NONE, "res 0,a" },	// 87
{ RES_R, 1, REG_B, INV, 8, TYPE_NONE, "res 1,b" },	// 88
{ RES_R, 1, REG_C, INV, 8, TYPE_NONE, "res 1,c" },	// 89
{ RES_R, 1, REG_D, INV, 8, TYPE_NONE, "res 1,d" },	// 8a
{ RES_R, 1, REG_E, INV, 8, TYPE_NONE, "res 1,e" },	// 8b
{ RES_R, 1, REG_H, INV, 8, TYPE_NONE, "res 1,h" },	// 8c
{ RES_R, 1, REG_L, INV, 8, TYPE_NONE, "res 1,l" },	// 8d
{ RES_MRR, 1, REG_HL, INV, 15, TYPE_NONE, "res 1,(hl)" },	// 8e
{ RES_R, 1, REG_A, INV, 8, TYPE_NONE, "res 1,a" },	// 8f
{ RES_R, 2, REG_B, INV, 8, TYPE_NONE, "res 2,b" },	// 90
{ RES_R, 2, REG_C, INV, 8, TYPE_NONE, "res 2,c" },	// 91
{ RES_R, 2, REG_D, INV, 8, TYPE_NONE, "res 2,d" },	// 92
{ RES_R, 2, REG_E, INV, 8, TYPE_NONE, "res 2,e" },	// 93
{ RES_R, 2, REG_H, INV, 8, TYPE_NONE, "res 2,h" },	// 94
{ RES_R, 2, REG_L, INV, 8, TYPE_NONE, "res 2,l" },	// 95
{ RES_MRR, 2, REG_HL, INV, 15, TYPE_NONE, "res 2,(hl)" },	// 96
{ RES_R, 2, REG_A, INV, 8, TYPE_NONE, "res 2,a" },	// 97
{ RES_R, 3, REG_B, INV, 8, TYPE_NONE, "res 3,b" },	// 98
{ RES_R, 3, REG_C, INV, 8, TYPE_NONE, "res 3,c" },	// 99
{ RES_R, 3, REG_D, INV, 8, TYPE_NONE, "res 3,d" },	// 9a
{ RES_R, 3, REG_E, INV, 8, TYPE_NONE, "res 3,e" },	// 9b
{ RES_R, 3, REG_H, INV, 8, TYPE_NONE, "res 3,h" },	// 9c
{ RES_R, 3, REG_L, INV, 8, TYPE_NONE, "res 3,l" },	// 9d
{ RES_MRR, 3, REG_HL, INV, 15, TYPE_NONE, "res 3,(hl)" },	// 9e
{ RES_R, 3, REG_A, INV, 8, TYPE_NONE, "res 3,a" },	// 9f
{ RES_R, 4, REG_B, INV, 8, TYPE_NONE, "res 4,b" },	// a0
{ RES_R, 4, REG_C, INV, 8, TYPE_NONE, "res 4,c" },	// a1
{ RES_R, 4, REG_D, INV, 8, TYPE_NONE, "res 4,d" },	// a2
{ RES_R, 4, REG_E, INV, 8, TYPE_NONE, "res 4,e" },	// a3
{ RES_R, 4, REG_H, INV, 8, TYPE_NONE, "res 4,h" },	// a4
{ RES_R, 4, REG_L, INV, 8, TYPE_NONE, "res 4,l" },	// a5
{ RES_MRR, 4, REG_HL, INV, 15, TYPE_NONE, "res 4,(hl)" },	// a6
{ RES_R, 4, REG_A, INV, 8, TYPE_NONE, "res 4,a" },	// a7
{ RES_R, 5, REG_B, INV, 8, TYPE_NONE, "res 5,b" },	// a8
{ RES_R, 5, REG_C, INV, 8, TYPE_NONE, "res 5,c" },	// a9
{ RES_R, 5, REG_D, INV, 8, TYPE_NONE, "res 5,d" },	// aa
{ RES_R, 5, REG_E, INV, 8, TYPE_NONE, "res 5,e" },	// ab
{ RES_R, 5, REG_H, INV, 8, TYPE_NONE, "res 5,h" },	// ac
{ RES_R, 5, REG_L, INV, 8, TYPE_NONE, "res 5,l" },	// ad
{ RES_MRR, 5, REG_HL, INV, 15, TYPE_NONE, "res 5,(hl)" },	// ae
{ RES_R, 5, REG_A, INV, 8, TYPE_NONE, "res 5,a" },	// af
{ RES_R, 6, REG_B, INV, 8, TYPE_NONE, "res 6,b" },	// b0
{ RES_R, 6, REG_C, INV, 8, TYPE_NONE, "res 6,c" },	// b1
{ RES_R, 6, REG_D, INV, 8, TYPE_NONE, "res 6,d" },	// b2
{ RES_R, 6, REG_E, INV, 8, TYPE_NONE, "res 6,e" },	// b3
{ RES_R, 6, REG_H, INV, 8, TYPE_NONE, "res 6,h" },	// b4
{ RES_R, 6, REG_L, INV, 8, TYPE_NONE, "res 6,l" },	// b5
{ RES_MRR, 6, REG_HL, INV, 15, TYPE_NONE, "res 6,(hl)" },	// b6
{ RES_R, 6, REG_A, INV, 8, TYPE_NONE, "res 6,a" },	// b7
{ RES_R, 7, REG_B, INV, 8, TYPE_NONE, "res 7,b" },	// b8
{ RES_R, 7, REG_C, INV, 8, TYPE_NONE, "res 7,c" },	// b9
{ RES_R, 7, REG_D, INV, 8, TYPE_NONE, "res 7,d" },	// ba
{ RES_R, 7, REG_E, INV, 8, TYPE_NONE, "res 7,e" },	// bb
{ RES_R, 7, REG_H, INV, 8, TYPE_NONE, "res 7,h" },	// bc
{ RES_R, 7, REG_L, INV, 8, TYPE_NONE, "res 7,l" },	// bd
{ RES_MRR, 7, REG_HL, INV, 15, TYPE_NONE, "res 7,(hl)" },	// be
{ RES_R, 7, REG_A, INV, 8, TYPE_NONE, "res 7,a" },	// bf
{ SET_R, 0, REG_B, INV, 8, TYPE_NONE, "set 0,b" },	// c0
{ SET_R, 0, REG_C, INV, 8, TYPE_NONE, "set 0,c" },	// c1
{ SET_R, 0, REG_D, INV, 8, TYPE_NONE, "set 0,d" },	// c2
{ SET_R, 0, REG_E, INV, 8, TYPE_NONE, "set 0,e" },	// c3
{ SET_R, 0, REG_H, INV, 8, TYPE_NONE, "set 0,h" },	// c4
{ SET_R, 0, REG_L, INV, 8, TYPE_NONE, "set 0,l" },	// c5
{ SET_MRR, 0, REG_HL, INV, 15, TYPE_NONE, "set 0,(hl)" },	// c6
{ SET_R, 0, REG_A, INV, 8, TYPE_NONE, "set 0,a" },	// c7
{ SET_R, 1, REG_B, INV, 8, TYPE_NONE, "set 1,b" },	// c8
{ SET_R, 1, REG_C, INV, 8, TYPE_NONE, "set 1,c" },	// c9
{ SET_R, 1, REG_D, INV, 8, TYPE_NONE, "set 1,d" },	// ca
{ SET_R, 1, REG_E, INV, 8, TYPE_NONE, "set 1,e" },	// cb
{ SET_R, 1, REG_H, INV, 8, TYPE_NONE, "set 1,h" },	// cc
{ SET_R, 1, REG_L, INV, 8, TYPE_NONE, "set 1,l" },	// cd
{ SET_MRR, 1, REG_HL, INV, 15, TYPE_NONE, "set 1,(hl)" },	// ce
{ SET_R, 1, REG_A, INV, 8, TYPE_NONE, "set 1,a" },	// cf
{ SET_R, 2, REG_B, INV, 8, TYPE_NONE, "set 2,b" },	// d0
{ SET_R, 2, REG_C, INV, 8, TYPE_NONE, "set 2,c" },	// d1
{ SET_R, 2, REG_D, INV, 8, TYPE_NONE, "set 2,d" },	// d2
{ SET_R, 2, REG_E, INV, 8, TYPE_NONE, "set 2,e" },	// d3
{ SET_R, 2, REG_H, INV, 8, TYPE_NONE, "set 2,h" },	// d4
{ SET_R, 2, REG_L, INV, 8, TYPE_NONE, "set 2,l" },	// d5
{ SET_MRR, 2, REG_HL, INV, 15, TYPE_NONE, "set 2,(hl)" },	// d6
{ SET_R, 2, REG_A, INV, 8, TYPE_NONE, "set 2,a" },	// d7
{ SET_R, 3, REG_B, INV, 8, TYPE_NONE, "set 3,b" },	// d8
{ SET_R, 3, REG_C, INV, 8, TYPE_NONE, "set 3,c" },	// d9
{ SET_R, 3, REG_D, INV, 8, TYPE_NONE, "set 3,d" },	// da
{ SET_R, 3, REG_E, INV, 8, TYPE_NONE, "set 3,e" },	// db
{ SET_R, 3, REG_H, INV, 8, TYPE_NONE, "set 3,h" },	// dc
{ SET_R, 3, REG_L, INV, 8, TYPE_NONE, "set 3,l" },	// dd
{ SET_MRR, 3, REG_HL, INV, 15, TYPE_NONE, "set 3,(hl)" },	// de
{ SET_R, 3, REG_A, INV, 8, TYPE_NONE, "set 3,a" },	// df
{ SET_R, 4, REG_B, INV, 8, TYPE_NONE, "set 4,b" },	// e0
{ SET_R, 4, REG_C, INV, 8, TYPE_NONE, "set 4,c" },	// e1
{ SET_R, 4, REG_D, INV, 8, TYPE_NONE, "set 4,d" },	// e2
{ SET_R, 4, REG_E, INV, 8, TYPE_NONE, "set 4,e" },	// e3
{ SET_R, 4, REG_H, INV, 8, TYPE_NONE, "set 4,h" },	// e4
{ SET_R, 4, REG_L, INV, 8, TYPE_NONE, "set 4,l" },	// e5
{ SET_MRR, 4, REG_HL, INV, 15, TYPE_NONE, "set 4,(hl)" },	// e6
{ SET_R, 4, REG_A, INV, 8, TYPE_NONE, "set 4,a" },	// e7
{ SET_R, 5, REG_B, INV, 8, TYPE_NONE, "set 5,b" },	// e8
{ SET_R, 5, REG_C, INV, 8, TYPE_NONE, "set 5,c" },	// e9
{ SET_R, 5, REG_D, INV, 8, TYPE_NONE, "set 5,d" },	// ea
{ SET_R, 5, REG_E, INV, 8, TYPE_NONE, "set 5,e" },	// eb
{ SET_R, 5, REG_H, INV, 8, TYPE_NONE, "set 5,h" },	// ec
{ SET_R, 5, REG_L, INV, 8, TYPE_NONE, "set 5,l" },	// ed
{ SET_MRR, 5, REG_HL, INV, 15, TYPE_NONE, "set 5,(hl)" },	// ee
{ SET_R, 5, REG_A, INV, 8, TYPE_NONE, "set 5,a" },	// ef
{ SET_R, 6, REG_B, INV, 8, TYPE_NONE, "set 6,b" },	// f0
{ SET_R, 6, REG_C, INV, 8, TYPE_NONE, "set 6,c" },	// f1
{ SET_R, 6, REG_D, INV, 8, TYPE_NONE, "set 6,d" },	// f2
{ SET_R, 6, REG_E, INV, 8, TYPE_NONE, "set 6,e" },	// f3
{ SET_R, 6, REG_H, INV, 8, TYPE_NONE, "set 6,h" },	// f4
{ SET_R, 6, REG_L, INV, 8, TYPE_NONE, "set 6,l" },	// f5
{ SET_MRR, 6, REG_HL, INV, 15, TYPE_NONE, "set 6,(hl)" },	// f6
{ SET_R, 6, REG_A, INV, 8, TYPE_NONE, "set 6,a" },	// f7
{ SET_R, 7, REG_B, INV, 8, TYPE_NONE, "set 7,b" },	// f8
{ SET_R, 7, REG_C, INV, 8, TYPE_NONE, "set 7,c" },	// f9
{ SET_R, 7, REG_D, INV, 8, TYPE_NONE, "set 7,d" },	// fa
{ SET_R, 7, REG_E, INV, 8, TYPE_NONE, "set 7,e" },	// fb
{ SET_R, 7, REG_H, INV, 8, TYPE_NONE, "set 7,h" },	// fc
{ SET_R, 7, REG_L, INV, 8, TYPE_NONE, "set 7,l" },	// fd
{ SET_MRR, 7, REG_HL, INV, 15, TYPE_NONE, "set 7,(hl)" },	// fe
{ SET_R, 7, REG_A, INV, 8, TYPE_NONE, "set 7,a" },	// ff