pjht/altair_emu
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Properly model tri-stated address bus during halt

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This commit is contained in:
pjht 2024-02-02 13:30:52 -06:00
parent b95c770acb
commit 406382c33a
Signed by: pjht
GPG Key ID: 7B5F6AFBEC7EE78E
2 changed files with 6 additions and 6 deletions
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8
src/cpu.rs
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@ -37,7 +37,7 @@ pub enum MemCycle {
Out(u16, u8), Out(u16, u8),
#[allow(unused)] #[allow(unused)]
Inta(u16), Inta(u16),
Hlta(u16), Hlta,
#[allow(unused)] #[allow(unused)]
IntaHlt(u16), IntaHlt(u16),
} }
@ -53,7 +53,7 @@ impl MemCycle {
Self::In(_) => Status::WO | Status::INP, Self::In(_) => Status::WO | Status::INP,
Self::Out(_, _) => Status::OUT, Self::Out(_, _) => Status::OUT,
Self::Inta(_) => Status::INTA | Status::WO | Status::M1, Self::Inta(_) => Status::INTA | Status::WO | Status::M1,
Self::Hlta(_) => Status::HLTA | Status::WO | Status::M1, Self::Hlta => Status::HLTA | Status::WO | Status::M1,
Self::IntaHlt(_) => Status::INTA | Status::HLTA | Status::WO | Status::M1, Self::IntaHlt(_) => Status::INTA | Status::HLTA | Status::WO | Status::M1,
} }
} }
@ -68,7 +68,7 @@ impl MemCycle {
Self::In(a) => a, Self::In(a) => a,
Self::Out(a, _) => a, Self::Out(a, _) => a,
Self::Inta(a) => a, Self::Inta(a) => a,
Self::Hlta(a) => a, Self::Hlta => 0xffff, // Address bus is tri-stated, altair has pullups
Self::IntaHlt(a) => a, Self::IntaHlt(a) => a,
} }
} }
@ -239,7 +239,7 @@ impl I8080 {
pub fn get_mem_cycle(&self) -> MemCycle { pub fn get_mem_cycle(&self) -> MemCycle {
if self.halted { if self.halted {
return MemCycle::Hlta(self.pc); return MemCycle::Hlta;
}; };
match self.cycle { match self.cycle {
MCycle::M1 => MemCycle::Fetch(self.pc), MCycle::M1 => MemCycle::Fetch(self.pc),

4
src/state.rs
View File

@ -123,7 +123,7 @@ impl EmuState {
self.fp_state.set_data(0); self.fp_state.set_data(0);
} }
MemCycle::Inta(_) => todo!(), MemCycle::Inta(_) => todo!(),
MemCycle::Hlta(_) => { MemCycle::Hlta => {
self.fp_state.set_addr(0xffff); self.fp_state.set_addr(0xffff);
self.fp_state.set_data(0xff); self.fp_state.set_data(0xff);
} }
@ -142,7 +142,7 @@ impl EmuState {
MemCycle::In(_) => 0, MemCycle::In(_) => 0,
MemCycle::Out(_, _) => 0, MemCycle::Out(_, _) => 0,
MemCycle::Inta(_) => todo!(), MemCycle::Inta(_) => todo!(),
MemCycle::Hlta(_) => { MemCycle::Hlta => {
self.running = false; self.running = false;
0 0
} }