diff --git a/src/cpu.rs b/src/cpu.rs
index 1358137..b83c3c4 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -37,7 +37,7 @@ pub enum MemCycle {
     Out(u16, u8),
     #[allow(unused)]
     Inta(u16),
-    Hlta(u16),
+    Hlta,
     #[allow(unused)]
     IntaHlt(u16),
 }
@@ -53,7 +53,7 @@ impl MemCycle {
             Self::In(_) => Status::WO | Status::INP,
             Self::Out(_, _) => Status::OUT,
             Self::Inta(_) => Status::INTA | Status::WO | Status::M1,
-            Self::Hlta(_) => Status::HLTA | Status::WO | Status::M1,
+            Self::Hlta => Status::HLTA | Status::WO | Status::M1,
             Self::IntaHlt(_) => Status::INTA | Status::HLTA | Status::WO | Status::M1,
         }
     }
@@ -68,7 +68,7 @@ impl MemCycle {
             Self::In(a) => a,
             Self::Out(a, _) => a,
             Self::Inta(a) => a,
-            Self::Hlta(a) => a,
+            Self::Hlta => 0xffff, // Address bus is tri-stated, altair has pullups
             Self::IntaHlt(a) => a,
         }
     }
@@ -239,7 +239,7 @@ impl I8080 {
 
     pub fn get_mem_cycle(&self) -> MemCycle {
         if self.halted {
-            return MemCycle::Hlta(self.pc);
+            return MemCycle::Hlta;
         };
         match self.cycle {
             MCycle::M1 => MemCycle::Fetch(self.pc),
diff --git a/src/state.rs b/src/state.rs
index 9d22204..8211607 100644
--- a/src/state.rs
+++ b/src/state.rs
@@ -123,7 +123,7 @@ impl EmuState {
                 self.fp_state.set_data(0);
             }
             MemCycle::Inta(_) => todo!(),
-            MemCycle::Hlta(_) => {
+            MemCycle::Hlta => {
                 self.fp_state.set_addr(0xffff);
                 self.fp_state.set_data(0xff);
             }
@@ -142,7 +142,7 @@ impl EmuState {
             MemCycle::In(_) => 0,
             MemCycle::Out(_, _) => 0,
             MemCycle::Inta(_) => todo!(),
-            MemCycle::Hlta(_) => {
+            MemCycle::Hlta => {
                 self.running = false;
                 0
             }