385 lines
9.4 KiB
Plaintext
385 lines
9.4 KiB
Plaintext
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EESchema Schematic File Version 4
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LIBS:motherboard-cache
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EELAYER 29 0
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EELAYER END
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$Descr USLetter 11000 8500
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encoding utf-8
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Sheet 2 4
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L Memory_RAM:AS6C4008-55PCN U?
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U 1 1 5D7FBFC9
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P 1450 1850
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AR Path="/5D7FBFC9" Ref="U?" Part="1"
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AR Path="/5D7E5BE3/5D7FBFC9" Ref="U3" Part="1"
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F 0 "U3" H 1700 3000 50 0000 C CNN
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F 1 "AS6C4008-55PCN" H 1850 2900 50 0000 C CNN
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F 2 "Package_DIP:DIP-32_W15.24mm_Socket" H 1450 1950 50 0001 C CNN
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F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C4008.pdf" H 1450 1950 50 0001 C CNN
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1 1450 1850
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1 0 0 -1
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$EndComp
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Text GLabel 950 950 0 50 3State ~ 0
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A0
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Text GLabel 950 1050 0 50 3State ~ 0
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A1
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Text GLabel 950 1150 0 50 3State ~ 0
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A2
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Text GLabel 950 1250 0 50 3State ~ 0
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A3
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Text GLabel 950 1350 0 50 3State ~ 0
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A4
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Text GLabel 950 1450 0 50 3State ~ 0
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A5
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Text GLabel 950 1550 0 50 3State ~ 0
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A6
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Text GLabel 950 1650 0 50 3State ~ 0
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A7
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Text GLabel 950 1750 0 50 3State ~ 0
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A8
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Text GLabel 950 1850 0 50 3State ~ 0
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A9
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Text GLabel 950 1950 0 50 3State ~ 0
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A10
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Text GLabel 950 2050 0 50 3State ~ 0
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A11
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Text GLabel 950 2150 0 50 3State ~ 0
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A12
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Text GLabel 950 2250 0 50 3State ~ 0
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A13
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Text GLabel 1950 2050 2 50 Input ~ 0
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~RD
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Text GLabel 1950 2150 2 50 Input ~ 0
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~WR
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$Comp
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L power:GND #PWR?
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U 1 1 5D7FBFE5
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P 1450 2950
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AR Path="/5D7FBFE5" Ref="#PWR?" Part="1"
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AR Path="/5D7E5BE3/5D7FBFE5" Ref="#PWR020" Part="1"
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F 0 "#PWR020" H 1450 2700 50 0001 C CNN
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F 1 "GND" H 1455 2777 50 0000 C CNN
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F 2 "" H 1450 2950 50 0001 C CNN
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F 3 "" H 1450 2950 50 0001 C CNN
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1 1450 2950
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1 0 0 -1
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$EndComp
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Text GLabel 1950 950 2 50 3State ~ 0
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D0
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Text GLabel 1950 1050 2 50 3State ~ 0
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D1
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Text GLabel 1950 1150 2 50 3State ~ 0
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D2
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Text GLabel 1950 1250 2 50 3State ~ 0
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D3
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Text GLabel 1950 1350 2 50 3State ~ 0
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D4
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Text GLabel 1950 1450 2 50 3State ~ 0
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D5
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Text GLabel 1950 1550 2 50 3State ~ 0
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D6
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Text GLabel 1950 1650 2 50 3State ~ 0
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D7
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$Comp
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L power:+5V #PWR?
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U 1 1 5D7FBFF3
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P 1450 750
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AR Path="/5D7FBFF3" Ref="#PWR?" Part="1"
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AR Path="/5D7E5BE3/5D7FBFF3" Ref="#PWR019" Part="1"
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F 0 "#PWR019" H 1450 600 50 0001 C CNN
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F 1 "+5V" H 1465 923 50 0000 C CNN
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F 2 "" H 1450 750 50 0001 C CNN
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F 3 "" H 1450 750 50 0001 C CNN
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1 1450 750
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1 0 0 -1
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$EndComp
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$Comp
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L Memory_RAM:AS6C4008-55PCN U?
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U 1 1 5D7FBFF9
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P 3200 1850
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AR Path="/5D7FBFF9" Ref="U?" Part="1"
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AR Path="/5D7E5BE3/5D7FBFF9" Ref="U4" Part="1"
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F 0 "U4" H 3450 3000 50 0000 C CNN
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F 1 "AS6C4008-55PCN" H 3600 2900 50 0000 C CNN
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F 2 "Package_DIP:DIP-32_W15.24mm_Socket" H 3200 1950 50 0001 C CNN
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F 3 "https://www.alliancememory.com/wp-content/uploads/pdf/AS6C4008.pdf" H 3200 1950 50 0001 C CNN
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1 3200 1850
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1 0 0 -1
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$EndComp
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Text GLabel 2700 950 0 50 3State ~ 0
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A0
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Text GLabel 2700 1050 0 50 3State ~ 0
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A1
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Text GLabel 2700 1150 0 50 3State ~ 0
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A2
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Text GLabel 2700 1250 0 50 3State ~ 0
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A3
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Text GLabel 2700 1350 0 50 3State ~ 0
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A4
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Text GLabel 2700 1450 0 50 3State ~ 0
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A5
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Text GLabel 2700 1550 0 50 3State ~ 0
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A6
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Text GLabel 2700 1650 0 50 3State ~ 0
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A7
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Text GLabel 2700 1750 0 50 3State ~ 0
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A8
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Text GLabel 2700 1850 0 50 3State ~ 0
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A9
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Text GLabel 2700 1950 0 50 3State ~ 0
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A10
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Text GLabel 2700 2050 0 50 3State ~ 0
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A11
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Text GLabel 2700 2150 0 50 3State ~ 0
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A12
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Text GLabel 2700 2250 0 50 3State ~ 0
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A13
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Text GLabel 3700 2050 2 50 Input ~ 0
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~RD
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Text GLabel 3700 2150 2 50 Input ~ 0
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~WR
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Text GLabel 3700 950 2 50 3State ~ 0
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D0
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Text GLabel 3700 1050 2 50 3State ~ 0
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D1
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Text GLabel 3700 1150 2 50 3State ~ 0
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D2
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Text GLabel 3700 1250 2 50 3State ~ 0
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D3
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Text GLabel 3700 1350 2 50 3State ~ 0
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D4
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Text GLabel 3700 1450 2 50 3State ~ 0
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D5
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Text GLabel 3700 1550 2 50 3State ~ 0
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D6
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Text GLabel 3700 1650 2 50 3State ~ 0
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D7
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$Comp
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L power:+5V #PWR?
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U 1 1 5D7FC023
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P 3200 750
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AR Path="/5D7FC023" Ref="#PWR?" Part="1"
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AR Path="/5D7E5BE3/5D7FC023" Ref="#PWR023" Part="1"
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F 0 "#PWR023" H 3200 600 50 0001 C CNN
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F 1 "+5V" H 3215 923 50 0000 C CNN
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F 2 "" H 3200 750 50 0001 C CNN
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F 3 "" H 3200 750 50 0001 C CNN
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1 3200 750
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1 0 0 -1
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$EndComp
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|
Text GLabel 5250 900 2 50 3State ~ 0
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D0
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Text GLabel 5250 1000 2 50 3State ~ 0
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D1
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Text GLabel 5250 1100 2 50 3State ~ 0
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D2
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Text GLabel 5250 1200 2 50 3State ~ 0
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D3
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Text GLabel 5250 1300 2 50 3State ~ 0
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D4
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Text GLabel 5250 1400 2 50 3State ~ 0
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D5
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Text GLabel 5250 1500 2 50 3State ~ 0
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D6
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Text GLabel 5250 1600 2 50 3State ~ 0
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D7
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$Comp
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L Memory_EEPROM:28C256 U?
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U 1 1 5D7FFB91
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P 4850 1800
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AR Path="/5D7FFB91" Ref="U?" Part="1"
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AR Path="/5D7E5BE3/5D7FFB91" Ref="U5" Part="1"
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F 0 "U5" H 5000 3000 50 0000 C CNN
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F 1 "28C256" H 5050 2900 50 0000 C CNN
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F 2 "Package_DIP:DIP-28_W15.24mm_Socket" H 4850 1800 50 0001 C CNN
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F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/doc0006.pdf" H 4850 1800 50 0001 C CNN
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1 4850 1800
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1 0 0 -1
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$EndComp
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$Comp
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|
L power:GND #PWR?
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|
U 1 1 5D7FFB97
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P 4850 2900
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AR Path="/5D7FFB97" Ref="#PWR?" Part="1"
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AR Path="/5D7E5BE3/5D7FFB97" Ref="#PWR028" Part="1"
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F 0 "#PWR028" H 4850 2650 50 0001 C CNN
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F 1 "GND" H 4855 2727 50 0000 C CNN
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F 2 "" H 4850 2900 50 0001 C CNN
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F 3 "" H 4850 2900 50 0001 C CNN
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1 4850 2900
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1 0 0 -1
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$EndComp
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|
$Comp
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|
L power:+5V #PWR?
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|
U 1 1 5D7FFB9D
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P 4850 700
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AR Path="/5D7FFB9D" Ref="#PWR?" Part="1"
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AR Path="/5D7E5BE3/5D7FFB9D" Ref="#PWR027" Part="1"
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F 0 "#PWR027" H 4850 550 50 0001 C CNN
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F 1 "+5V" H 4865 873 50 0000 C CNN
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F 2 "" H 4850 700 50 0001 C CNN
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F 3 "" H 4850 700 50 0001 C CNN
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|
1 4850 700
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|
1 0 0 -1
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|
$EndComp
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||
|
Text GLabel 4450 900 0 50 3State ~ 0
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A0
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Text GLabel 4450 1000 0 50 3State ~ 0
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A1
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Text GLabel 4450 1100 0 50 3State ~ 0
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A2
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|
Text GLabel 4450 1200 0 50 3State ~ 0
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A3
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||
|
Text GLabel 4450 1300 0 50 3State ~ 0
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A4
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||
|
Text GLabel 4450 1400 0 50 3State ~ 0
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||
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A5
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|
Text GLabel 4450 1500 0 50 3State ~ 0
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A6
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Text GLabel 4450 1600 0 50 3State ~ 0
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A7
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Text GLabel 4450 1700 0 50 3State ~ 0
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A8
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Text GLabel 4450 1800 0 50 3State ~ 0
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A9
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Text GLabel 4450 1900 0 50 3State ~ 0
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A10
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Text GLabel 4450 2000 0 50 3State ~ 0
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A11
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|
Text GLabel 4450 2100 0 50 3State ~ 0
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A12
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|
Text GLabel 4450 2200 0 50 3State ~ 0
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||
|
A13
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||
|
Text GLabel 4450 2600 0 50 Input ~ 0
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|
~RD
|
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|
Text GLabel 4450 2500 0 50 Input ~ 0
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~WR
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|
Text HLabel 4450 2300 0 50 Input ~ 0
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MEM_A14
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Text HLabel 2700 2750 0 50 Input ~ 0
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MEM_A18
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Text HLabel 2700 2650 0 50 Input ~ 0
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|
MEM_A17
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|
Text HLabel 2700 2550 0 50 Input ~ 0
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|
MEM_A16
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|
Text HLabel 2700 2450 0 50 Input ~ 0
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|
MEM_A15
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|
Text HLabel 2700 2350 0 50 Input ~ 0
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|
MEM_A14
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|
Text HLabel 950 2750 0 50 Input ~ 0
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|
MEM_A18
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|
Text HLabel 950 2650 0 50 Input ~ 0
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|
MEM_A17
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|
Text HLabel 950 2550 0 50 Input ~ 0
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|
MEM_A16
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|
Text HLabel 950 2450 0 50 Input ~ 0
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||
|
MEM_A15
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|
Text HLabel 950 2350 0 50 Input ~ 0
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||
|
MEM_A14
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|
Text HLabel 4450 2700 0 50 Input ~ 0
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||
|
MEM_ROM
|
||
|
Text HLabel 3700 1950 2 50 Input ~ 0
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||
|
MEM_512K2
|
||
|
Text HLabel 1950 1950 2 50 Input ~ 0
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||
|
MEM_512K1
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||
|
$Comp
|
||
|
L power:GND #PWR024
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|
U 1 1 5D8280A2
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P 3200 2950
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|
F 0 "#PWR024" H 3200 2700 50 0001 C CNN
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|
F 1 "GND" H 3205 2777 50 0000 C CNN
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|
F 2 "" H 3200 2950 50 0001 C CNN
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||
|
F 3 "" H 3200 2950 50 0001 C CNN
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||
|
1 3200 2950
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||
|
1 0 0 -1
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$EndComp
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||
|
NoConn ~ -1950 6250
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||
|
NoConn ~ 600 3550
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|
$Comp
|
||
|
L power:+5V #PWR?
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|
U 1 1 5D8ABD55
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|
P 2750 3550
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|
AR Path="/5D8ABD55" Ref="#PWR?" Part="1"
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||
|
AR Path="/5D7E5BE3/5D8ABD55" Ref="#PWR021" Part="1"
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||
|
F 0 "#PWR021" H 2750 3400 50 0001 C CNN
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||
|
F 1 "+5V" H 2765 3723 50 0000 C CNN
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||
|
F 2 "" H 2750 3550 50 0001 C CNN
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||
|
F 3 "" H 2750 3550 50 0001 C CNN
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||
|
1 2750 3550
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||
|
1 0 0 -1
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||
|
$EndComp
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||
|
$Comp
|
||
|
L power:GND #PWR?
|
||
|
U 1 1 5D8ABD5B
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||
|
P 2750 3750
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||
|
AR Path="/5D8ABD5B" Ref="#PWR?" Part="1"
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||
|
AR Path="/5D7E5BE3/5D8ABD5B" Ref="#PWR022" Part="1"
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||
|
F 0 "#PWR022" H 2750 3500 50 0001 C CNN
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||
|
F 1 "GND" H 2755 3577 50 0000 C CNN
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||
|
F 2 "" H 2750 3750 50 0001 C CNN
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||
|
F 3 "" H 2750 3750 50 0001 C CNN
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||
|
1 2750 3750
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||
|
1 0 0 -1
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||
|
$EndComp
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||
|
$Comp
|
||
|
L Device:C_Small C?
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||
|
U 1 1 5D8ABD61
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||
|
P 2750 3650
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||
|
AR Path="/5D8ABD61" Ref="C?" Part="1"
|
||
|
AR Path="/5D7E5BE3/5D8ABD61" Ref="C3" Part="1"
|
||
|
F 0 "C3" H 2842 3696 50 0000 L CNN
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||
|
F 1 "0.1u" H 2842 3605 50 0000 L CNN
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||
|
F 2 "Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm" H 2750 3650 50 0001 C CNN
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||
|
F 3 "~" H 2750 3650 50 0001 C CNN
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||
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1 2750 3650
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||
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1 0 0 -1
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||
|
$EndComp
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||
|
$Comp
|
||
|
L power:+5V #PWR?
|
||
|
U 1 1 5D8AC5F3
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||
|
P 3250 3550
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||
|
AR Path="/5D8AC5F3" Ref="#PWR?" Part="1"
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||
|
AR Path="/5D7E5BE3/5D8AC5F3" Ref="#PWR025" Part="1"
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||
|
F 0 "#PWR025" H 3250 3400 50 0001 C CNN
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||
|
F 1 "+5V" H 3265 3723 50 0000 C CNN
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||
|
F 2 "" H 3250 3550 50 0001 C CNN
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||
|
F 3 "" H 3250 3550 50 0001 C CNN
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||
|
1 3250 3550
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||
|
1 0 0 -1
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||
|
$EndComp
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||
|
$Comp
|
||
|
L power:GND #PWR?
|
||
|
U 1 1 5D8AC5F9
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||
|
P 3250 3750
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||
|
AR Path="/5D8AC5F9" Ref="#PWR?" Part="1"
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||
|
AR Path="/5D7E5BE3/5D8AC5F9" Ref="#PWR026" Part="1"
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||
|
F 0 "#PWR026" H 3250 3500 50 0001 C CNN
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||
|
F 1 "GND" H 3255 3577 50 0000 C CNN
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||
|
F 2 "" H 3250 3750 50 0001 C CNN
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||
|
F 3 "" H 3250 3750 50 0001 C CNN
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||
|
1 3250 3750
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||
|
1 0 0 -1
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||
|
$EndComp
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||
|
$Comp
|
||
|
L Device:C_Small C?
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||
|
U 1 1 5D8AC5FF
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||
|
P 3250 3650
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||
|
AR Path="/5D8AC5FF" Ref="C?" Part="1"
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||
|
AR Path="/5D7E5BE3/5D8AC5FF" Ref="C4" Part="1"
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||
|
F 0 "C4" H 3342 3696 50 0000 L CNN
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||
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F 1 "0.1u" H 3342 3605 50 0000 L CNN
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||
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F 2 "Capacitor_THT:C_Disc_D3.0mm_W1.6mm_P2.50mm" H 3250 3650 50 0001 C CNN
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||
|
F 3 "~" H 3250 3650 50 0001 C CNN
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||
|
1 3250 3650
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||
|
1 0 0 -1
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||
|
$EndComp
|
||
|
$EndSCHEMATC
|