Caleb Zulawski 11c3eefa35 Manually implement for supported lanes

2022-02-24 18:03:40 -08:00

..

masks

Manually implement for supported lanes

2022-02-24 18:03:40 -08:00

ops

impl Op<&'_ RHS> for &'_ LHS

2021-12-01 15:45:01 -08:00

vector

Update crates/core_simd/src/vector/float.rs

2022-01-24 20:11:17 -05:00

vendor

Uncomment AVX512 byte vector conversions

2021-11-26 13:48:52 -08:00

comparisons.rs

Sprinkle the crate with #[must_use]

2021-11-14 12:11:35 -08:00

core_simd_docs.md

Restructure crate as core module

2021-09-18 23:26:10 -07:00

fmt.rs

Restructure crate as core module

2021-09-18 23:26:10 -07:00

intrinsics.rs

Omit Simd::cast during bootstrap

2022-01-27 10:59:23 -08:00

iter.rs

Restructure crate as core module

2021-09-18 23:26:10 -07:00

lane_count.rs

Attempt to support to 64 lanes

2021-11-23 15:19:01 -08:00

lib.rs

Genericize to_int_unchecked

2022-02-03 03:46:16 -08:00

masks.rs

Use bitmask trait

2022-02-24 18:02:39 -08:00

math.rs

Drop splats for Simd<T, _>

2021-12-01 15:40:53 -08:00

mod.rs

Remove Select trait

2021-12-04 05:54:15 +00:00

ops.rs

Annotate signed type in int_divrem_guard

2022-01-20 19:22:14 -08:00

reduction.rs

Generically implement horizontal_{and,or,xor}

2021-11-24 08:07:41 -08:00

round.rs

Genericize to_int_unchecked

2022-02-03 03:46:16 -08:00

select.rs

Remove Select trait

2021-12-04 05:54:15 +00:00

swizzle.rs

Sprinkle the crate with #[must_use]

2021-11-14 12:11:35 -08:00

to_bytes.rs

Restructure crate as core module

2021-09-18 23:26:10 -07:00

vector.rs

Omit Simd::cast during bootstrap

2022-01-27 10:59:23 -08:00

vendor.rs

Rewrite Arm transmutes, reading std::arch closer

2021-11-12 16:56:14 -08:00