Limit address from CPU to 24 bits
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parent
6dc1d5d798
commit
6066b2d239
12
src/m68k.rs
12
src/m68k.rs
@ -62,13 +62,6 @@ impl Display for DetailedBusError {
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impl Error for DetailedBusError {}
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impl Error for DetailedBusError {}
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// pub trait Bus: Debug {
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// fn read_word(&mut self, address: u32) -> Result<u16, BusError>;
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// fn read_byte(&mut self, address: u32) -> Result<u8, BusError>;
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// fn write_word(&mut self, address: u32, data: u16) -> Result<(), BusError>;
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// fn write_byte(&mut self, address: u32, data: u8) -> Result<(), BusError>;
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// }
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#[derive(Debug)]
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#[derive(Debug)]
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pub struct M68K {
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pub struct M68K {
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dregs: [u32; 8],
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dregs: [u32; 8],
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@ -1194,6 +1187,7 @@ impl M68K {
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fn read_address(&mut self, address: u32, size: Size) -> Result<u32, DetailedBusError> {
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fn read_address(&mut self, address: u32, size: Size) -> Result<u32, DetailedBusError> {
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// println!("READ {:x}, {:?}", address, size);
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// println!("READ {:x}, {:?}", address, size);
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let address = address & 0xFF_FFFF;
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match size {
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match size {
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Size::Byte => Ok(u32::from(self.read_byte(address)?)),
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Size::Byte => Ok(u32::from(self.read_byte(address)?)),
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Size::Word => Ok(u32::from(self.read_word(address)?)),
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Size::Word => Ok(u32::from(self.read_word(address)?)),
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@ -1223,6 +1217,7 @@ impl M68K {
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}
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}
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fn read_byte(&mut self, address: u32) -> Result<u8, DetailedBusError> {
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fn read_byte(&mut self, address: u32) -> Result<u8, DetailedBusError> {
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let address = address & 0xFF_FFFF;
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self.bus.read_byte(address).map_err(|_| DetailedBusError {
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self.bus.read_byte(address).map_err(|_| DetailedBusError {
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address,
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address,
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cause: BusErrorCause::ReadingByte,
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cause: BusErrorCause::ReadingByte,
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@ -1230,6 +1225,7 @@ impl M68K {
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}
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}
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fn write_byte(&mut self, address: u32, data: u8) -> Result<(), DetailedBusError> {
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fn write_byte(&mut self, address: u32, data: u8) -> Result<(), DetailedBusError> {
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let address = address & 0xFF_FFFF;
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self.bus
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self.bus
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.write_byte(address, data)
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.write_byte(address, data)
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.map_err(|_| DetailedBusError {
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.map_err(|_| DetailedBusError {
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@ -1239,6 +1235,7 @@ impl M68K {
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}
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}
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fn read_word(&mut self, address: u32) -> Result<u16, DetailedBusError> {
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fn read_word(&mut self, address: u32) -> Result<u16, DetailedBusError> {
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let address = address & 0xFF_FFFF;
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if address & 0x1 != 0 {
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if address & 0x1 != 0 {
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self.trap(3)?;
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self.trap(3)?;
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}
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}
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@ -1249,6 +1246,7 @@ impl M68K {
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}
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}
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fn write_word(&mut self, address: u32, data: u16) -> Result<(), DetailedBusError> {
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fn write_word(&mut self, address: u32, data: u16) -> Result<(), DetailedBusError> {
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let address = address & 0xFF_FFFF;
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if address & 0x1 != 0 {
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if address & 0x1 != 0 {
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self.trap(3)?;
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self.trap(3)?;
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}
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}
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