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Limit address from CPU to 24 bits

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This commit is contained in:
pjht 2023-03-18 17:51:34 -05:00
parent 6dc1d5d798
commit 6066b2d239
Signed by: pjht
GPG Key ID: 7B5F6AFBEC7EE78E
1 changed files with 5 additions and 7 deletions
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12
src/m68k.rs
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@ -62,13 +62,6 @@ impl Display for DetailedBusError {
impl Error for DetailedBusError {}
// pub trait Bus: Debug {
// fn read_word(&mut self, address: u32) -> Result<u16, BusError>;
// fn read_byte(&mut self, address: u32) -> Result<u8, BusError>;
// fn write_word(&mut self, address: u32, data: u16) -> Result<(), BusError>;
// fn write_byte(&mut self, address: u32, data: u8) -> Result<(), BusError>;
// }
#[derive(Debug)]
pub struct M68K {
dregs: [u32; 8],
@ -1194,6 +1187,7 @@ impl M68K {
fn read_address(&mut self, address: u32, size: Size) -> Result<u32, DetailedBusError> {
// println!("READ {:x}, {:?}", address, size);
let address = address & 0xFF_FFFF;
match size {
Size::Byte => Ok(u32::from(self.read_byte(address)?)),
Size::Word => Ok(u32::from(self.read_word(address)?)),
@ -1223,6 +1217,7 @@ impl M68K {
}
fn read_byte(&mut self, address: u32) -> Result<u8, DetailedBusError> {
let address = address & 0xFF_FFFF;
self.bus.read_byte(address).map_err(|_| DetailedBusError {
address,
cause: BusErrorCause::ReadingByte,
@ -1230,6 +1225,7 @@ impl M68K {
}
fn write_byte(&mut self, address: u32, data: u8) -> Result<(), DetailedBusError> {
let address = address & 0xFF_FFFF;
self.bus
.write_byte(address, data)
.map_err(|_| DetailedBusError {
@ -1239,6 +1235,7 @@ impl M68K {
}
fn read_word(&mut self, address: u32) -> Result<u16, DetailedBusError> {
let address = address & 0xFF_FFFF;
if address & 0x1 != 0 {
self.trap(3)?;
}
@ -1249,6 +1246,7 @@ impl M68K {
}
fn write_word(&mut self, address: u32, data: u16) -> Result<(), DetailedBusError> {
let address = address & 0xFF_FFFF;
if address & 0x1 != 0 {
self.trap(3)?;
}