26 lines
554 B
Verilog
Executable File
26 lines
554 B
Verilog
Executable File
//16 byte RAM used for KT8
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module ram (clk_i,
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address_i,
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in_i,
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out_o,
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we_i);
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input clk_i, we_i;
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input [3:0] address_i;
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input [7:0] in_i;
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output [7:0] out_o;
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//CK - Changed array to 0-15 from 15-0
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//not sure if it matters, but this seems to be the standard
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reg [7:0] mem [0:15];
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always @(posedge clk_i)
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if (we_i) mem[address_i]=in_i;
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//output is not clocked, always reflects current memory addresses
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assign out_o=mem[address_i];
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endmodule
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