41 lines
1.2 KiB
Verilog
Executable File
41 lines
1.2 KiB
Verilog
Executable File
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//testbench for program counter.
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`include "pc.v"
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module pc_tb();
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reg clk, rst, jump_up, jump_down;
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reg [3:0] jump_distance;
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wire [7:0] pc_out;
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//instantiate device under test
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pc dut(.clk_i (clk),
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.rst_i (rst),
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.jump_up_i (jump_up),
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.jump_down_i (jump_down),
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.jump_distance_i (jump_distance),
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.count_o (pc_out) );
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initial begin
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$monitor ("clk=%b,rst=%b,jump_up=%b,jump_down=%b,jump_dist=%b,out=%b",
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clk, rst, jump_up, jump_down, jump_distance, pc_out);
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#5 clk=0; rst=1; jump_up=0; jump_down=0; jump_distance=0;
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//come out of reset and clock twice
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$display("Try increment");
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#5 rst=0; #5 clk=1; #5 clk=0; #5 clk=1; #5 clk=0;
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if (pc_out!=2) $error("Failed Increment");
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$display("Try jump up");
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#5 jump_distance=5; jump_up=1;
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#5 clk=1; #5 clk=0;
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if(pc_out!=7) $error("Failed Jump Up");
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$display("Try jump down");
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#5 jump_up=0; jump_down=1; jump_distance=6;
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#5 clk=1; #5 clk=0;
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if( pc_out!=1) $error("Failed Jump Down");
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$display("Try reset");
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#5 rst=1;
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#5 clk=1; #5 clk=0; #5 clk=1; #5 clk=0;
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if(pc_out!=0) $error("Failed Reset Hold");
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end
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endmodule
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