33 lines
1.0 KiB
Verilog
Executable File
33 lines
1.0 KiB
Verilog
Executable File
module pc_testbench();
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logic clk, rst, jump_up, jump_down;
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logic [15:0] pc_out;
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logic [3:0] jump_distance;
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//instantiate device under test
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program_counter dut(clk, rst,
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jump_up, jump_down, jump_distance,
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pc_out );
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initial begin
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clk=0; rst=1; jump_up=0; jump_down=0;
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jump_distance=0;
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#10;
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//come out of reset and clock twice
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rst=0; #5;
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clk=1; #5; clk=0; #5; clk=1; #5; clk=0; #5;
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assert (pc_out===1) else $error("Failed Increment");
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//try jump up
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jump_distance=5; jump_up=1; #5;
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clk=1; #5; clk=0; #5;
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assert (pc_out===7) else $error("Failed Jump Up");
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//try jump down
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jump_up=0; jump_down=1; jump_distance=6; #5;
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clk=1; #5; clk=0; #5;
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assert( pc_out===1) else $error("Failed Jump Down");
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//hold in reset
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rst=1; #5;
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clk=1; #5; clk=0; #5; clk=1; #5; clk=0; #5;
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assert (pc_out===0) else $error("Failed Reset Hold");
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end
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endmodule
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