65 lines
1.5 KiB
Verilog
Executable File
65 lines
1.5 KiB
Verilog
Executable File
//KT8 with RAM and testbench code
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`include "cpu.v"
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`include "ram.v"
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`include "rom.v"
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module kt8();
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reg clk;
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reg rst;
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wire [7:0] rom_address;
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wire [7:0] rom_data;
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wire [4:0] ram_address; //includes mapped I/O
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wire [7:0] ram_out;
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wire [7:0] ram_in;
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wire ram_we;
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cpu kt8_cpu(.clk_i (clk),
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.rst_i (rst),
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.p_address_o (rom_address),
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.p_data_i (rom_data),
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.ram_address_o (ram_address),
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.ram_data_i (ram_out),
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.ram_data_o (ram_in),
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.ram_we_o (ram_we) );
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//program memory 256 bytes
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rom progmem(.address_i (rom_address),
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.out_o (rom_data) );
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//actual RAM is first 16 bytes of data address space
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//needs a mux or enable to handle high 16 bytes
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ram datamem(.clk_i (clk),
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.address_i (ram_address[3:0]),
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.in_i (ram_in),
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.out_o (ram_out),
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.we_i (ram_we) );
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//testbench, load a program into ROM and cycle the clock
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initial begin
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$readmemb("ram.txt", datamem.mem);
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$readmemb("fib.txt", progmem.mem);
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$dumpfile("kt8.dump");
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$dumpvars();
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rst=1; clk=0;
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#5 rst=0;
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$monitor ("PC=%h,I=%b,A=%h,B=%h,R=%h,ram[0]=%h,ram[1]=%h,rst=%h",
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rom_address,
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rom_data,
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kt8_cpu.a_out,
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kt8_cpu.b_out,
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ram_in,
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datamem.mem[0],
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datamem.mem[1],
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rst );
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while (kt8_cpu.hlt == 0) begin
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#5 clk=1;
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#5 clk=0;
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end
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end
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endmodule
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