52 lines
1.5 KiB
Verilog
Executable File
52 lines
1.5 KiB
Verilog
Executable File
//KT8 instruction decoder
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//Lots of random logic to do the correct thing for each instruction
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module data_control (instruction_i, //the current instruction
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b_value_o, //B can be ORd with imediate
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b_current_i,
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load_a_o, //controls loading of registers
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load_b_o,
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load_r_o,
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ram_wr_o, //also control RAM write
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ram_data_i );
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input [7:0] instruction_i, ram_data_i, b_current_i;
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output reg [7:0] b_value_o;
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output reg load_b_o;
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output wire load_a_o, load_r_o, ram_wr_o;
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reg jump_up_o, jump_down_o;
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reg [3:0] jump_distance_o;
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//I = 010aaaaa : save to memory
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assign ram_wr_o = (instruction_i[7:5] == 3'b010) ? 1 : 0;
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//I=000aaaaa : load RAM to A
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assign load_a_o = (instruction_i[7:5] == 3'b000) ? 1 : 0;
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//I=1000xxxx : ALU op, load R
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assign load_r_o = (instruction_i[7:4] == 4'b1000) ? 1 : 0;
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//what to do with register B
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always @(*)
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if (instruction_i[7:4] == 4'b0110) begin
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//LOWBITS
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b_value_o = {b_current_i[7:4], instruction_i[3:0]};
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load_b_o = 1;
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end else if (instruction_i[7:4] == 4'b0111) begin
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//HIGHBITS
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b_value_o = {instruction_i[3:0], b_current_i[3:0]};
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load_b_o = 1;
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end else if (instruction_i[7:5] == 3'b001) begin
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//load B from RAM
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b_value_o = ram_data_i;
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load_b_o = 1;
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end else begin
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//leave B alone
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b_value_o = 0;
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load_b_o = 0;
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end
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endmodule
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