86 lines
2.8 KiB
Verilog
Executable File
86 lines
2.8 KiB
Verilog
Executable File
//The KT8 CPU core, not including program memory or RAM
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`include "pc.v"
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`include "datareg.v"
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`include "alu.v"
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`include "program_control.v"
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`include "data_control.v"
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module cpu(clk_i,
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rst_i,
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p_address_o,
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p_data_i,
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ram_address_o,
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ram_data_i,
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ram_data_o,
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ram_we_o );
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input clk_i, rst_i;
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input [7:0] p_data_i;
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input [7:0] ram_data_i;
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output [7:0] p_address_o;
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output [4:0] ram_address_o;
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output [7:0] ram_data_o;
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output ram_we_o;
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//CPU internal buses and signals
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wire jump_up, jump_down, load_a, load_b, load_r, pcrst, rst, hlt;
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wire [3:0] jump_distance;
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wire [7:0] a_out, b_in, b_out, r_in;
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//registers
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datareg A(.clk_i (clk),
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.rst_i (rst_i),
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.en_i (load_a),
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.in_i (ram_data_i), //A reg always loaded from RAM
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.out_o (a_out) );
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datareg B(.clk_i (clk),
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.rst_i (rst_i),
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.en_i (load_b),
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.in_i (b_in),
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.out_o (b_out) );
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datareg R(.clk_i (clk),
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.rst_i (rst_i),
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.en_i (load_r),
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.in_i (r_in),
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.out_o (ram_data_o) ); //R reg outputs direct to RAM
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//program counter
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pc PC(.clk_i (clk),
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.rst_i (pcrst),
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.jump_up_i (jump_up),
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.jump_down_i (jump_down),
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.jump_distance_i (jump_distance),
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.count_o (p_address_o) );
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//ALU, calcs based on A and B, results go to R
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//opcode is always low 4 bits of instruction
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alu ALU(.a_i (a_out),
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.b_i (b_out),
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.op_i (p_data_i[3:0]),
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.r_o (r_in) );
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// contains all the combinatorial logic to control registers, RAM and PC based
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// on current instruction
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program_control PCTRL (.instruction_i (p_data_i), //the current instruction
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.r_value_i (ram_data_o), //needed for R=0 test
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.rst_i (rst_i),
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.jump_up_o (jump_up), //control of PC
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.jump_down_o (jump_down),
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.jump_distance_o (jump_distance),
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.rst_o (rst),
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.hlt_o (hlt) );
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data_control DCTRL (.instruction_i (p_data_i), //the current instruction
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.b_value_o (b_in), //B can be ORd with imediate
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.b_current_i (b_out),
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.load_a_o (load_a), //controls loading of registers
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.load_b_o (load_b),
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.load_r_o (load_r),
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.ram_wr_o (ram_we_o), //also control RAM write
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.ram_data_i (ram_data_i) );
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//RAM address is always lower 5 bits of instruction (for valid instructions)
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assign ram_address_o = p_data_i[4:0];
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assign pcrst = rst_i || rst;
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assign clk = ~hlt && clk_i;
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endmodule
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