26 lines
438 B
Verilog
Executable File
26 lines
438 B
Verilog
Executable File
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//testbench for alu
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`include "alu.v"
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module alu_tb();
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reg [7:0] a, b;
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reg [3:0] op;
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wire [7:0] r;
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//instantiate device under test
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alu dut(.a_i (a),
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.b_i (b),
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.op_i (op),
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.r_o (r) );
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initial begin
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$monitor ("a=%b,b=%b,op=%b,r=%b",
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a, b, op, r);
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a=0; b=0; op=0;
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#5 a=3; b=5;
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#5 op=1;
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end
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endmodule
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