183 lines
2.5 KiB
Verilog
183 lines
2.5 KiB
Verilog
module ins_dec(ins,carry,zero,aload,bload,dsel,rfload,str,opsel,jump,hlt);
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input [3:0] ins;
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input carry,zero;
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output aload,bload,dsel,rfload,str,opsel,jump,hlt;
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wire ins;
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reg aload,bload,dsel,rfload,opsel,str,jump,hlt;
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always @(*)
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if (ins==0) begin
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aload=1;
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bload=0;
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dsel=0;
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rfload=0;
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str=0;
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opsel=0;
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jump=0;
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hlt=0;
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end else if (ins==1) begin
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aload=0;
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bload=1;
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dsel=0;
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rfload=0;
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str=0;
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opsel=0;
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jump=0;
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hlt=0;
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end else if (ins==2) begin
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aload=1;
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bload=0;
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dsel=1;
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rfload=0;
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str=0;
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opsel=0;
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jump=0;
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hlt=0;
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end else if (ins==3) begin
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aload=0;
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bload=1;
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dsel=1;
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rfload=0;
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str=0;
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opsel=0;
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jump=0;
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hlt=0;
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end else if (ins==4) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=1;
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str=0;
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opsel=0;
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jump=0;
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hlt=0;
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end else if (ins==5) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=1;
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str=0;
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opsel=1;
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jump=0;
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hlt=0;
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end else if (ins==6) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=0;
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str=1;
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opsel=0;
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jump=1;
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hlt=0;
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end else if (ins==7) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=0;
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str=1;
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opsel=0;
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jump=1;
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hlt=0;
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end else if (ins==8 && carry) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=0;
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str=1;
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opsel=0;
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jump=1;
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hlt=0;
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end else if (ins==9 && !carry) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=0;
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str=1;
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opsel=0;
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jump=1;
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end else if (ins==10 && zero) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=0;
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str=1;
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opsel=0;
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jump=1;
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hlt=0;
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end else if (ins==11 && !zero) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=0;
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str=1;
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opsel=0;
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jump=1;
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hlt=0;
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end else if (ins==12) begin
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aload=0;
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bload=0;
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dsel=0;
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rfload=0;
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str=1;
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opsel=0;
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jump=1;
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hlt=1;
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end else begin
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bload=0;
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dsel=0;
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aload=0;
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rfload=0;
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str=0;
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opsel=0;
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jump=0;
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hlt=0;
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end
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endmodule
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module insdec_tb();
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reg [3:0] ins;
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reg carry, zero;
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wire aload,bload,dsel,rfload,opsel,jump,hlt;
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ins_dec insdec(.ins (ins),
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.carry (carry),
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.zero (zero),
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.aload (aload),
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.bload (bload),
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.dsel (dsel),
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.rfload (rfload),
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.opsel (opsel),
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.jump (jump),
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.hlt (hlt)
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);
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initial begin
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$monitor("ins=%h,carry=%b,zero=%b,aload=%b,bload=%b,dsel=%b,rfload=%b,opsel=%b,jump=%b,hlt=%b",
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ins,
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carry,
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zero,
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aload,
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bload,
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dsel,
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rfload,
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opsel,
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jump,
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hlt);
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ins=0;
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carry=0;
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zero=0;
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#1 ins=1;
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#1 ins=2;
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#1 ins=3;
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#1 ins=4;
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#1 ins=5;
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#1 ins=6;
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#1 ins=7;
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#1 ins=8;carry=1;
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#1 ins=8;carry=0;
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#1 ins=9;carry=1;
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#1 ins=9;carry=0;
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#1 ins=10;zero=1;
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#1 ins=10;zero=0;
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#1 ins=11;zero=1;
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#1 ins=11;zero=0;
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#1 ins=12;
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end
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endmodule
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