21 lines
458 B
Verilog
21 lines
458 B
Verilog
// Data Register for CPU1. Used for A,B,and R
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// Original 8 bit design by Charlie Krauter for KT8.
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// 4 bit register with reset and enable
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module datareg(clk_i,
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rst_i,
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en_i,
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in_i,
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out_o );
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input clk_i, rst_i, en_i;
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input [3:0] in_i;
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output [3:0] out_o;
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reg [3:0] out_o;
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always @(posedge clk_i, posedge rst_i)
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if (rst_i) out_o<=0;
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else if (en_i) out_o<=in_i;
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endmodule
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