48 lines
1.2 KiB
Verilog
48 lines
1.2 KiB
Verilog
`include "datareg.v"
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`include "alu.v"
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`include "insdec.v"
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`include "pc.v"
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module cpu(clk_i,rst_i,p_addr,p_data,r_addr,r_data_i,r_data_o,we);
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input clk_i,rst_i;
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input [7:0] p_data;
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input [3:0] r_data_i;
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output [3:0] p_addr,r_addr,r_data_o;
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output we;
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wire load_a,load_b,load_rf,dsel,aluop,jmp,hlt,rst,clk;
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wire [3:0] reg_in,a_out,b_out,r_in;
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pc PC(.clk_i (clk),
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.rst_i (rst),
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.jump_i (jmp),
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.jump_v (p_data[3:0]),
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.count_o (p_addr) );
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datareg A(.clk_i (clk),
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.rst_i (rst),
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.en_i (load_a),
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.in_i (reg_in),
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.out_o (a_out) );
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datareg B(.clk_i (clk),
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.rst_i (rst),
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.en_i (load_b),
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.in_i (reg_in),
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.out_o (b_out) );
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datareg R(.clk_i (clk),
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.rst_i (rst),
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.en_i (load_rf),
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.in_i (r_in),
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.out_o (r_data_o) );
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alu ALU(.a (a_out),
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.b (b_out),
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.op (aluop),
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.r (r_in));
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insdec DECODER(.ins (p_data[7:4]),
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.carry (1'b0),
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.zero (1'b0),
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.aload (load_a),
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.bload (load_b),
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.dsel (dsel),
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.rfload (load_rf),
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.str (we),
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.opsel (aluop),
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.jump (jmp),
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.hlt (hlt) );
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endmodule |