13 lines
163 B
Verilog
13 lines
163 B
Verilog
module alu(a,b,op,r);
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input [3:0] a,b;
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input op;
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output [3:0] r;
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wire a,b,op;
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reg r;
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always @(*)
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if (op==0) begin
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r=a+b;
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end else begin
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r=a-b;
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end
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endmodule |