stuff

cpu/alu.v

@@ -0,0 +1,32 @@
+module alu(a,b,op,r);
+input [3:0] a,b;
+input op;
+output [3:0] r;
+wire a,b,op;
+reg r;
+always @(*)
+	if (op==0) begin
+		r=a+b;
+	end else begin
+		r=a-b;
+	end
+endmodule
+module alu_tb();
+reg [3:0] a,b;
+reg op;
+wire [3:0] r;
+alu tb_alu(.a (a),
+.b (b),
+.op (op),
+.r (r)
+);
+initial begin
+$monitor("a=%h,b=%h,op=%h,r=%h",
+		  	a,
+		  	b,
+		  	op,
+		  	r);
+#1 a=2;b=2;op=0;
+#1 a=3;b=2;op=1;
+end
+endmodule

cpu/datareg.v

@@ -0,0 +1,20 @@
+// Data Register for CPU1. Used for A,B,and R
+// Original 8 bit design by Charlie Krauter for KT8.
+// 4 bit register with reset and enable
+
+module datareg(clk_i,
+               rst_i,
+               en_i,
+               in_i,
+               out_o );
+  input clk_i, rst_i, en_i;
+  input [3:0] in_i;
+  output [3:0] out_o;
+
+  reg [3:0] out_o;
+					   
+  always @(posedge clk_i, posedge rst_i)
+    if (rst_i) out_o<=0;
+    else if (en_i) out_o<=in_i;
+
+endmodule