pjht/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of https://github.com/pjht/verilog

Browse Source
This commit is contained in:
pjht 2017-02-28 17:41:03 -06:00
commit 9e25481eec
5 changed files with 74 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -3,3 +3,4 @@
._*
*.out
*.dump
*.bat

21
cpu/alu.v
View File

@ -10,23 +10,4 @@ always @(*)
end else begin
r=a-b;
end
endmodule
module alu_tb();
reg [3:0] a,b;
reg op;
wire [3:0] r;
alu tb_alu(.a (a),
.b (b),
.op (op),
.r (r)
);
initial begin
$monitor("a=%h,b=%h,op=%h,r=%h",
a,
b,
op,
r);
#1 a=2;b=2;op=0;
#1 a=3;b=2;op=1;
end
endmodule
endmodule

48
cpu/cpu.v Normal file
View File

@ -0,0 +1,48 @@
`include "datareg.v"
`include "alu.v"
`include "insdec.v"
`include "pc.v"
module cpu(clk_i,rst_i,p_addr,p_data,r_addr,r_data_i,r_data_o,we);
input clk_i,rst_i;
input [7:0] p_data;
input [3:0] r_data_i;
output [3:0] p_addr,r_addr,r_data_o;
output we;
wire load_a,load_b,load_rf,dsel,aluop,jmp,hlt,rst,clk;
wire [3:0] reg_in,a_out,b_out,r_in;
pc PC(.clk_i (clk),
.rst_i (rst),
.jump_i (jmp),
.jump_v (p_data[3:0]),
.count_o (p_addr) );
datareg A(.clk_i (clk),
.rst_i (rst),
.en_i (load_a),
.in_i (reg_in),
.out_o (a_out) );
datareg B(.clk_i (clk),
.rst_i (rst),
.en_i (load_b),
.in_i (reg_in),
.out_o (b_out) );
datareg R(.clk_i (clk),
.rst_i (rst),
.en_i (load_rf),
.in_i (r_in),
.out_o (r_data_o) );
alu ALU(.a (a_out),
.b (b_out),
.op (aluop),
.r (r_in));
insdec DECODER(.ins (p_data[7:4]),
.carry (1'b0),
.zero (1'b0),
.aload (load_a),
.bload (load_b),
.dsel (dsel),
.rfload (load_rf),
.str (we),
.opsel (aluop),
.jump (jmp),
.hlt (hlt) );
endmodule

52
cpu/insdec.v
View File

@ -1,4 +1,4 @@
module ins_dec(ins,carry,zero,aload,bload,dsel,rfload,str,opsel,jump,hlt);
module insdec(ins,carry,zero,aload,bload,dsel,rfload,str,opsel,jump,hlt);
input [3:0] ins;
input carry,zero;
output aload,bload,dsel,rfload,str,opsel,jump,hlt;
@ -119,7 +119,7 @@ always @(*)
rfload=0;
str=1;
opsel=0;
jump=1;
jump=0;
hlt=1;
end else begin
bload=0;
@ -132,51 +132,3 @@ always @(*)
hlt=0;
end
endmodule
module insdec_tb();
reg [3:0] ins;
reg carry, zero;
wire aload,bload,dsel,rfload,opsel,jump,hlt;
ins_dec insdec(.ins (ins),
.carry (carry),
.zero (zero),
.aload (aload),
.bload (bload),
.dsel (dsel),
.rfload (rfload),
.opsel (opsel),
.jump (jump),
.hlt (hlt)
);
initial begin
$monitor("ins=%h,carry=%b,zero=%b,aload=%b,bload=%b,dsel=%b,rfload=%b,opsel=%b,jump=%b,hlt=%b",
ins,
carry,
zero,
aload,
bload,
dsel,
rfload,
opsel,
jump,
hlt);
ins=0;
carry=0;
zero=0;
#1 ins=1;
#1 ins=2;
#1 ins=3;
#1 ins=4;
#1 ins=5;
#1 ins=6;
#1 ins=7;
#1 ins=8;carry=1;
#1 ins=8;carry=0;
#1 ins=9;carry=1;
#1 ins=9;carry=0;
#1 ins=10;zero=1;
#1 ins=10;zero=0;
#1 ins=11;zero=1;
#1 ins=11;zero=0;
#1 ins=12;
end
endmodule

22
cpu/pc.v Normal file
View File

@ -0,0 +1,22 @@
// Program Counter for CPU1
// Original design by Charlie Krauter for KT8
// 4 bit counter with reset. Can also jump.
module pc(clk_i,
rst_i,
jump_i,
jump_v,
count_o );
input clk_i, rst_i, jump_i;
input [3:0] jump_v;
output [3:0] count_o;
reg [3:0] count_o;
always @(posedge clk_i, posedge rst_i)
if (rst_i) count_o<=0;
else if (jump_i) count_o<=jump_i;
else count_o<=count_o+1;
endmodule