29 lines
622 B
Coq
29 lines
622 B
Coq
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//testbench for KT8 RAM
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`include "ram.v"
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module ram_tb();
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reg clk, we;
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reg [3:0] address;
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reg [7:0] ram_in;
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wire [7:0] ram_out;
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//instantiate device under test
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ram dut(.clk_i (clk),
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.address_i (address),
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.in_i (ram_in),
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.out_o (ram_out),
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.we_i (we) );
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initial $readmemh("ramtest.txt", dut.mem);
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initial begin
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$monitor ("clk=%b,Address=%b,ram_in=%b,ram_out=%b,WE=%b", clk, address, ram_in, ram_out, we);
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#5 clk=0; address=1; ram_in=10; we=0;
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#5 we=1;
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#5 clk=1;
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#5 we=0;
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end
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endmodule
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