75 lines
1.6 KiB
Systemverilog
75 lines
1.6 KiB
Systemverilog
module t64_system ();
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logic [63:0] din,addr,dout;
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logic [1:0] width;
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logic clk,reset,write,intr,intack,unhandledexcept;
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integer i;
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ram RAM (
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.din(dout),
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.dout(din),
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.ain(addr),
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.width(width),
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.write(write),
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.clk(clk)
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);
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t64 CPU (
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.din(din),
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.clk(clk),
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.reset(reset),
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.intr(intr),
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.aouttrue(addr),
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.dout(dout),
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.widthtrue(width),
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.writetrue(write),
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.intack(intack),
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.unhandledexcept(unhandledexcept)
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);
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wire[127:0] insword;
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assign insword={CPU.opl8,CPU.opf8};
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wire[63:0] dbus;
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assign dbus=(write) ? dout : din;
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initial begin
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$dumpfile("dumps/t64.lxt");
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$dumpvars(10,RAM,CPU,t64_system,RAM.ram[22]);
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for (i=0;i<16;i=i+1) begin
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$dumpvars(0,CPU.rf.rf.regs[i]);
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end
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for (i=0;i<65536;i=i+1) begin
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RAM.ram[i]=0;
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end
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$readmemh("prog.hex",RAM.ram);
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RAM.ram[16'hA000>>3]=64'hB001;
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RAM.ram[16'hB000>>3]=64'hC001;
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RAM.ram[16'hC000>>3]=64'hD001;
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RAM.ram[16'hD000>>3]=64'hE001;
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RAM.ram[16'hE000>>3]=64'hF001;
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RAM.ram[16'hF000>>3]=64'h0000;
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RAM.ram[16'hF008>>3]=64'h0001;
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RAM.ram[16'hF078>>3]=64'hF001;
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// CPU.memmu.fetcher.pl6p=64'hA000;
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intr=1'b0; clk=1'b0; reset=1'b1; #1;
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reset=1'b0;
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// repeat(32) begin
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// clk=1'b1; #1;
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// clk=1'b0; #1;
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// if(RAM.ram[CPU.pc>>3]==64'hFF)
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// $finish;
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// end
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// end
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// intr=1'b1;
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forever begin
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clk=1'b1; #1;
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clk=1'b0; #1;
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if((CPU.phase==0 && din==64'hFF) || unhandledexcept) begin
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$finish;
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end
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if(intack) begin
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intr=1'b0;
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end
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end
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end
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endmodule
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