54 lines
809 B
Systemverilog
54 lines
809 B
Systemverilog
module regfile_tb();
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logic [63:0] din,rdaout,rdbout;
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logic [3:0] wrsel,rdasel,rdbsel;
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logic [1:0] width;
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logic reset,wr;
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regfile DUT (
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.din(din),
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.rdaout(rdaout),
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.rdbout(rdbout),
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.wrsel(wrsel),
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.rdasel(rdasel),
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.rdbsel(rdbsel),
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.reset(reset),
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.wr(wr),
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.width(width)
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);
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initial begin
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$dumpfile("dumps/regfile.vcd");
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$dumpvars(0,regfile_tb);
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width=2'h0;
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din=64'h0;
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reset=1'b0;
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wr=1'b0;
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wrsel=4'h0;
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rdasel=4'h0;
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rdbsel=4'h0;
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#1
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width=2'h0;
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din=64'h0;
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reset=1'b1;
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wr=1'b0;
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wrsel=4'h0;
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rdasel=4'h0;
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rdbsel=4'h0;
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#1
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reset=1'b0;
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#1
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din=64'hFFFFFFFFFFFFFFFF;
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wr=1'b1;
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#1
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wr=1'b0;
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#1
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reset=1'b1;
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#1
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reset=1'b0;
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#1
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$finish;
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end
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endmodule
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