33 lines
625 B
Systemverilog
33 lines
625 B
Systemverilog
module regfile_if_tb();
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logic[63:0] din,retaddr,imm,aluout,rdaout,rdbout;
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logic[1:0] width;
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logic reset,wr,retload,immload,aluload,setr;
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logic[3:0] wrsel,rdasel,rdbsel;
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regfile_if DUT (
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.din(din),
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.retaddr(retaddr),
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.imm(imm),
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.aluout(aluout),
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.rdaout(rdaout),
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.rdbout(rdbout),
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.width(width),
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.reset(reset),
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.wr(wr),
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.retload(retload),
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.immload(immload),
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.aluload(aluload),
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.setr(setr),
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.wrsel(wrsel),
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.rdasel(rdasel),
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.rdbsel(rdbsel)
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);
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initial begin
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$dumpfile("dumps/regfile_if.vcd");
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$dumpvars(0,regfile_if_tb);
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end
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endmodule
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