46 lines
615 B
Systemverilog
46 lines
615 B
Systemverilog
module pc_tb();
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logic clk,reset,jump;
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logic[63:0] jumpaddr,retaddr,pc;
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pc DUT (
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.clk(clk),
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.reset(reset),
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.jump(jump),
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.jumpaddr(jumpaddr),
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.retaddr(retaddr),
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.pc(pc)
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);
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initial begin
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$dumpfile("dumps/pc.vcd");
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$dumpvars(0,pc_tb);
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clk=1'b0;
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reset=1'b0;
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jump=1'b0;
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jumpaddr=64'h0;
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#1;
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reset=1'b1;
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#1;
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reset=1'b0;
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#1
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clk=1'b1;
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#1;
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clk=1'b0;
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#1
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clk=1'b1;
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#1;
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clk=1'b0;
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jumpaddr=64'h60;
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jump=1'b1;
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#1;
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clk=1'b1;
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#1;
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clk=1'b0;
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reset=1'b1;
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#1;
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reset=1'b0;
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end
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endmodule
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