78 lines
1007 B
Systemverilog
78 lines
1007 B
Systemverilog
module mmu_tb ();
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reg [63:0] addrin,din,pl6pdata;
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reg reset,memcycle,clk,pl6pwr;
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wire [63:0] addrout;
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wire [1:0] width;
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wire pgstrctwalk,pgft;
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mmu DUT(
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.addrin(addrin),
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.din(din),
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.pl6pdata(pl6pdata),
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.reset(reset),
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.memcycle(memcycle),
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.clk(clk),
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.pl6pwr(pl6pwr),
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.addrout(addrout),
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.width(width),
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.pgstrctwalk(pgstrctwalk),
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.pgft(pgft)
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);
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initial begin
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$dumpfile("dumps/mmu.vcd");
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$dumpvars(0,mmu_tb);
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addrin=64'h0;
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din=64'h0;
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pl6pdata=64'h0;
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reset=1'b0;
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memcycle=1'b0;
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clk=1'b0;
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pl6pwr=1'b0;
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#1;
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reset=1'b1;
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#1;
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reset=1'b0;
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pl6pdata=64'h1000;
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pl6pwr=1'b1;
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clk=1'b1;
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#1;
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clk=1'b0;
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pl6pwr=1'b0;
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#1;
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din=64'h2001;
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memcycle=1'b1;
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clk=1'b1;
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#1
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clk=1'b0;
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#1
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din=64'h3000;
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clk=1'b1;
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#1
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clk=1'b0;
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#1
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din=64'h4001;
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clk=1'b1;
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#1;
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clk=1'b0;
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#1;
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din=64'h5001;
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clk=1'b1;
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#1;
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clk=1'b0;
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#1;
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din=64'h6001;
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clk=1'b1;
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#1;
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clk=1'b0;
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#1;
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din=64'ha001;
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clk=1'b1;
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#1;
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clk=1'b0;
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#1;
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end
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endmodule
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