33 lines
788 B
Systemverilog
33 lines
788 B
Systemverilog
module tlb #(parameter length = 4096) (input [63:0] pageno,wrpageno,tableentry,
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input [12:0] wraddr,
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input write,
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input reset,
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output logic hit,
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output logic[63:0] data);
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logic[64:0] pgnos[length-1:0];
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logic[64:0] entries[length-1:0];
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integer i=0;
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always @ (posedge write or reset) begin
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if (reset) begin
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for (i=0;i<length;i=i+1)
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pgnos[i]=64'h0;
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entries[i]=64'h0;
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end
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else if (write) begin
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pgnos[wrpageno]=wrpageno;
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entries[wrpageno]=tableentry;
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end
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end
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always @ ( * ) begin
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data=0;
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hit=0;
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for (i=0;i<length;i=i+1)
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if ((pgnos[i]==pageno)&&entries[i][0]&&~hit) begin
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data=entries[i];
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hit=1;
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end
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end
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endmodule
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