32 lines
742 B
Systemverilog
Executable File
32 lines
742 B
Systemverilog
Executable File
module regfile (input[63:0] din,
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input[1:0] width,
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input reset,wr,
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input[3:0] wrsel,rdasel,rdbsel,
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output wire[63:0] rdaout,rdbout);
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reg[63:0] regs[16];
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always @ (wr or reset) begin
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if(reset) begin
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integer i;
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for(i=0; i<16; i=i+1) begin
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regs[i]<=0;
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end
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end;
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if(wr) begin
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if(width==0) begin
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regs[wrsel]<=din&64'hFF;
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end
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if(width==1) begin
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regs[wrsel]<=din&64'hFFFF;
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end
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if(width==2) begin
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regs[wrsel]<=din&64'hFFFFFFFF;
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end
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if(width==3) begin
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regs[wrsel]<=din;
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end
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end
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end
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assign rdaout=regs[rdasel];
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assign rdbout=regs[rdbsel];
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endmodule
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