102 lines
2.1 KiB
Systemverilog
102 lines
2.1 KiB
Systemverilog
module control (input[63:0] opf8,opl8,
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input exec,carry,zero,
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output logic[63:0] imm,
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output wire[7:0] aluop,
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output wire[3:0] wrsel,rdasel,rdbsel,
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output reg[1:0] width,
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output wire retload,
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output reg regwr,memwr,aluload,jump,immload,memaddr,pointer,specialwr,iret);
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wire[7:0] opcode;
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wire[3:0] addrmode;
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reg[1:0] opwidth;
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reg regwrop,memwrop,jumpop,specialwrop;
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assign opcode=opf8[7:0];
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assign addrmode=opf8[15:12];
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assign wrsel=opf8[11:8];
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assign rdasel=opf8[23:20];
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assign rdbsel=opf8[19:16];
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assign aluop=opf8[31:24];
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assign regwr=regwrop&exec;
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assign memwr=memwrop&exec;
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assign jump=jumpop&exec;
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assign specialwr=(opcode==18)&exec;
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assign iret=(opcode==19)&exec;
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assign retload=(opcode==8'h11);
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always @ ( * ) begin
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case (opcode)
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0: opwidth=0;
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1: opwidth=1;
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2: opwidth=2;
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3: opwidth=3;
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4: opwidth=0;
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5: opwidth=1;
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6: opwidth=2;
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7: opwidth=3;
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8: opwidth=0;
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9: opwidth=1;
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10: opwidth=2;
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11: opwidth=3;
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default: opwidth=0;
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endcase
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if (exec)
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width=opwidth;
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else
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width=3;
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case (opcode)
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0: regwrop=1;
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1: regwrop=1;
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2: regwrop=1;
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3: regwrop=1;
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8: regwrop=1;
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9: regwrop=1;
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10: regwrop=1;
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11: regwrop=1;
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17: regwrop=1;
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default: regwrop=0;
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endcase
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immload=0;
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memaddr=0;
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pointer=0;
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case (addrmode)
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0: immload=1;
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1: memaddr=1;
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2: pointer=1;
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8: immload=1;
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default: ;
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endcase
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if(addrmode==8) begin
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imm[31:0]=opf8[63:32];
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imm[63:32]=opl8[31:0];
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end
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else begin
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imm[39:0]=opf8[63:24];
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imm[63:40]=opl8[31:0];
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end
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case (opcode)
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4: memwrop=1;
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5: memwrop=1;
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6: memwrop=1;
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7: memwrop=1;
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default: memwrop=0;
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endcase
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case (opcode)
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8: aluload=1;
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9: aluload=1;
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10: aluload=1;
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11: aluload=1;
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default: aluload=0;
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endcase
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case (opcode)
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12: jumpop=1;
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13: jumpop=1&zero;
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14: jumpop=1&~zero;
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15: jumpop=1&carry;
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16: jumpop=1&~carry;
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17: jumpop=1;
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default: jumpop=0;
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endcase
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end
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endmodule // control
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