38 lines
525 B
Systemverilog
38 lines
525 B
Systemverilog
module alu_tb();
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logic [63:0] a,b,r;
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logic [7:0] op;
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logic [1:0] width;
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logic cin,zero,carry,setcarry,setr;
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alu DUT (
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.a(a),
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.b(b),
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.op(op),
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.cin(cin),
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.width(width),
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.r(r),
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.zero(zero),
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.carry(carry),
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.setcarry(setcarry),
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.setr(setr)
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);
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initial begin
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$dumpfile("dumps/alu.vcd");
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$dumpvars(0,alu_tb);
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width=2'h0;
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cin=1'b0;
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a=64'hFF;
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b=64'h0;
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op=8'h0;
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#1;
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a=8'hA8;
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b=8'h22;
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op=8'h1;
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#1;
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$finish;
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end
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endmodule
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