50 lines
806 B
Systemverilog
50 lines
806 B
Systemverilog
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module tlb_tb ();
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logic [63:0] pageno,wrpageno,tableentry,data;
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logic [12:0] wraddr;
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logic write,hit,reset;
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tlb DUT (
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.pageno(pageno),
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.wrpageno(wrpageno),
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.tableentry(tableentry),
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.wraddr(wraddr),
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.write(write),
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.reset(reset),
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.hit(hit),
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.data(data)
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);
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initial begin
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$dumpfile("dumps/tlb.lxt");
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$dumpvars(0,tlb_tb);
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pageno=64'h0;
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wrpageno=64'h0;
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tableentry=64'h0;
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wraddr=12'h0;
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write=1'b0;
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reset=1'b0;
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#1;
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reset=1'b1;
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#1
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reset=1'b0;
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write=1'b1;
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#1;
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write=1'b0;
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tableentry=64'h5001;
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#1;
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write=1'b1;
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#1;
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write=1'b0;
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#1;
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pageno=64'h1;
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#1;
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wrpageno=64'h1;
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wraddr=12'h1;
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tableentry=64'h6001;
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write=1'b1;
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#1;
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write=1'b0;
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#1;
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end
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endmodule
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