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Fix JLCPCB clearance issues

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pjht 2023-02-05 13:40:49 -06:00
parent 838418afc9
commit ea5402c6e7
Signed by: pjht
GPG Key ID: 7B5F6AFBEC7EE78E
2 changed files with 740 additions and 615 deletions
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stencil_trainer.kicad_pcb
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stencil_trainer.kicad_pro
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@ -103,7 +103,7 @@
"allow_blind_buried_vias": false,
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.0,
"min_clearance": 0.32999999999999996,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,