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Add license notice to schematic and PCB design files and update silkscreen notice

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This commit is contained in:
pjht 2023-03-03 09:32:42 -06:00
parent 6a2f61bed7
commit b7b5ea4e60
Signed by: pjht
GPG Key ID: 7B5F6AFBEC7EE78E
2 changed files with 6 additions and 2 deletions
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6
stencil_trainer_1.kicad_pcb
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@ -9,6 +9,8 @@
(title "Stencil Trainer 1 (48 pin i2c GPIO expander)")
(date "2023-03-03")
(rev "v1.0.0-dev2")
(comment 1 "Licensed under CERN-OHL-S version 2")
(comment 2 "Copyright Peter Terpstra, 2023")
)
(layers
@ -3368,8 +3370,8 @@
(gr_rect (start 45.37 168.39) (end 51.37 174.39) (layer "F.SilkS") (width 0.15) (fill solid) (tstamp 0929ceda-a80b-43bf-8078-478ecbde7a2d))
(gr_rect (start 91.5 97) (end 33 175) (layer "Edge.Cuts") (width 0.1) (fill none) (tstamp 0cc2535e-8a02-4c75-961d-48271d454d3c))
(gr_text "Licensed under CERN-OHL-S v2" (at 66.4 119.3) (layer "B.SilkS") (tstamp 2b900a22-48b6-47af-87b0-4a5c84b44556)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
(gr_text "Copyright Peter Terpstra, 2023\nLicensed under CERN-OHL-S v2" (at 78.9 120) (layer "B.SilkS") (tstamp 2b900a22-48b6-47af-87b0-4a5c84b44556)
(effects (font (size 1 1) (thickness 0.15)) (justify left mirror))
)
(gr_text "J3-5 pinout: (pin 1 is the pin closest to U2)\npin 1: GND\npin 2: PWR (3.3v-5v)\npin 3: SDA\npin 4: SCL" (at 80 108.2) (layer "B.SilkS") (tstamp 752e711b-bc09-4065-93c9-d1987f5bc8d4)
(effects (font (size 1 1) (thickness 0.15)) (justify left mirror))

2
stencil_trainer_1.kicad_sch
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@ -8,6 +8,8 @@
(title "Stencil Trainer 1 (48 pin i2c GPIO expander) ")
(date "2023-03-03")
(rev "v1.0.0-dev2")
(comment 1 "Licensed under CERN-OHL-S version 2")
(comment 2 "Copyright Peter Terpstra, 2023")
)
(lib_symbols