183 lines
5.0 KiB
Ruby
Executable File
183 lines
5.0 KiB
Ruby
Executable File
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require_relative "rcircuit_lib"
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class ALU < Device
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def initialize(init_args={},width)
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#define inputs and outputs
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define_port('a', width)
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define_port('b', width)
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define_port('op', 4)
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define_port('out', width)
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#connect ports in init arguments
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init_assign(init_args)
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#create internal components
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define_device("mux", Mux.new(8, 4).sel(op)
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.in0(a + b)
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.in1(a - b)
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.in2(a & b)
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.in3(a | b)
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.in4(a ^ b)
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.in5(!a)
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.in6(!b)
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.in7(a)
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.in8(b)
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.in9(a << 1)
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.in10(a >> 1)
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.in11(a + 1)
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.in12(a - 1)
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.in13(0)
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.in14(0)
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.in15(0) )
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mux.out.connect(out)
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end
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end
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def ALU.test
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puts "ALU test:"
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a=Port.new(8)
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b=Port.new(8)
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op=Port.new(4)
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alu=ALU.new({"a"=>a,"b"=>b,"op"=>op},8)
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dbg=Dbg.new({"a"=>a,"b"=>b,"op"=>op,"out"=>alu.out},true)
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a.value=3
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b.value=10
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dbg.add_trigger("op")
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for i in (0..15) do
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op.value=i
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end
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end
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class KT8Decoder < Device
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def initialize(init_args={})
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define_port("ins",8)
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init_assign(init_args)
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define_port("aen")
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define_port("ben")
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define_port("ren")
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define_port("wr")
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define_port("rbsel")
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define_port("den")
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@ins4to7=ins.slice(4..7)
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@ins0to3=ins.slice(0..3)
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define_device("dec", Decoder.new(4)
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.sel(@ins4to7)
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.en(1)
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.o0(aen)
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.o1(ben)
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.o2(wr)
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.o3(rbsel)
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.o8(ren)
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.o11(den) )
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define_device("dec1", Decoder.new(4).sel(@ins0to3).en(den) )
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end
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def on_change(new_val)
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puts "ins:#{ins.value},ins[5:7]:#{@ins5to7.value},ins[4:7]:#{@ins4to7.value}"
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if @ins5to7.value==0
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puts "5to7=0"
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aen.value=1
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ben.value=0
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ren.value=0
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wr.value=0
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rbsel.value=0
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end
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if @ins5to7.value==1
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puts "5to7=1"
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aen.value=0
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ben.value=1
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ren.value=0
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wr.value=0
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rbsel.value=0
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end
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if @ins5to7.value==2
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puts "5to7=2"
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aen.value=0
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ben.value=0
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ren.value=0
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wr.value=1
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rbsel.value=0
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end
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if @ins4to7.value==6
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puts "4to7=6"
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aen.value=0
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ben.value=0
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ren.value=0
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wr.value=0
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rbsel.value=1
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end
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if @ins4to7.value==7
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puts "4to7=7"
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aen.value=0
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ben.value=0
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ren.value=0
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wr.value=0
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rbsel.value=2
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end
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if @ins4to7.value==8
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puts "4to7=8"
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aen.value=0
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ben.value=0
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ren.value=1
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wr.value=0
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rbsel.value=0
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end
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end
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end
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#start of KT8 parts
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class KT8 < Device
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def initialize(init_args={})
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define_port("clk")
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define_port("rst")
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define_port("dout",8)
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define_port("ins",8)
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init_assign(init_args)
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define_port("wr")
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define_port("paddr",8)
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define_port("daddr",5)
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define_port("din",8)
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define_device("dec", KT8Decoder.new().ins(ins).wr(wr))
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define_device("pc", Counter.new(8).clk(clk).rst(rst).load(0).out(paddr))
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define_device("reg_a", Reg.new(8).clk(clk).rst(rst).en(dec.aen))
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define_device("reg_b",Reg.new(8).clk(clk).rst(rst).en(dec.ben))
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define_device("reg_r",Reg.new(8).clk(clk).rst(rst).en(dec.ren))
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define_device("alu",ALU.new(8).a(reg_a.out).b(reg_b.out).op(ins.slice(0..3)).out(reg_r.in))
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daddr.connect(ins.slice(0..4))
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din.connect(reg_r.out)
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#reg A input is always from data memory
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reg_a.in(dout)
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#reg B can be from memory or current value combined with immediate bits
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low_bit_combine = reg_b.out.slice(4..7).join(ins.slice(0..3))
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high_bit_combine = ins.out.slice(0..3).join(reg_b.out.slice(0..3))
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reg_b_source = Mux.new(8,1).in0(dout).in1(low_bit_combine).sel(dec.rbsel)
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reg_b.in(reg_b_source.out)
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end
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end
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clk=Port.new
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rst=Port.new
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prog_mem=Ram.new(8,8)
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data_mem=Ram.new(8,5)
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kt8=KT8.new("clk"=>clk,"rst"=>rst,"dout"=>data_mem.out,"ins"=>prog_mem.out)
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prog_mem.addr(kt8.paddr).clk(clk).wr(0).in(0)
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data_mem.addr(kt8.daddr).clk(clk).wr(kt8.wr).in(kt8.din)
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dbg=Dbg.new("paddr"=>kt8.paddr,"daddr"=>kt8.daddr,"aval"=>kt8.reg_a.out,"rval"=>kt8.reg_r.out,"ins"=>kt8.ins,"aen"=>kt8.dec.aen,"ben"=>kt8.dec.ben,"ren"=>kt8.dec.ren,"wr"=>kt8.dec.wr,"rbsel"=>kt8.dec.rbsel,"aluop"=>prog_mem.out.slice(0..3))
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prog_mem[0]="00000000"
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prog_mem[1]="10000111"
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prog_mem[2]="01000001"
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data_mem[0]="1011"
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rst.value=0
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clk.value=0
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rst.value=1
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rst.value=0
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dbg.out
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clk.value=1
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dbg.out
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clk.value=0
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clk.value=1
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dbg.out
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clk.value=0
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clk.value=1
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dbg.out
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puts "Putting.."
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puts data_mem[1].inspect
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