Add VCD tets
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@ -1,6 +1,9 @@
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## Creates VCD files from port states
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class VCD
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# @!attribute [w] fd
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# @api private
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attr_writer :fd
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# @param filename [String] The filename to output to
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# @param timescale [String] The timescale
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def initialize(filename, timescale="1ps")
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@ -28,7 +31,12 @@ class VCD
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write_port_state(portname)
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end
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@fd.puts "$end"
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@fd.puts "\#0"
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@fd.puts "#0"
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@portmap.each do |name,port|
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port.add_callback do |value|
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write_port_state(name)
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end
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end
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end
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# Stop logging
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@ -49,16 +57,13 @@ class VCD
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@idmap[portname] = @id
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@id=@id.next()
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@portmap[portname] = port
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port.add_callback do |value|
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write_port_state(portname)
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end
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end
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# Advance x timesteps
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# @param timesteps [Integer] The number of timesteps to advance
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def advance(timesteps)
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@time += timesteps
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@fd.puts "\##{@time.to_s}"
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@fd.puts "##{@time.to_s}"
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end
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private
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43
spec/vcd_spec.rb
Normal file
43
spec/vcd_spec.rb
Normal file
@ -0,0 +1,43 @@
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describe VCD do
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it "Outputs VCD files" do
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a=Port.new(1)
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b=Port.new(1)
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gate=XorGate.new(a,b)
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vcd=VCD.new("vcd_test.vcd")
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obj=double()
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allow(obj).to receive(:puts)
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allow(obj).to receive(:close)
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vcd.fd=obj
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`rm vcd_test.vcd`
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vcd.attach(a,"a")
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vcd.attach(b,"b")
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vcd.attach(gate.out, "out")
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expect(obj).to receive(:puts).with("$scope module TOP $end")
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expect(obj).to receive(:puts).with("$var wire 1 a a $end")
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expect(obj).to receive(:puts).with("$var wire 1 b b $end")
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expect(obj).to receive(:puts).with("$var wire 1 c out $end")
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expect(obj).to receive(:puts).with("$upscope $end")
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expect(obj).to receive(:puts).with("$enddefinitions $end")
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expect(obj).to receive(:puts).with("$dumpvars")
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expect(obj).to receive(:puts).with("0a")
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expect(obj).to receive(:puts).with("0b")
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expect(obj).to receive(:puts).with("0c")
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expect(obj).to receive(:puts).with("$end")
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expect(obj).to receive(:puts).with("#0")
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vcd.start
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expect(obj).to receive(:puts).with("1a")
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expect(obj).to receive(:puts).with("1c")
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a.setval(1)
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expect(obj).to receive(:puts).with("#1")
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vcd.advance(1)
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expect(obj).to receive(:puts).with("1b")
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expect(obj).to receive(:puts).with("0c")
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b.setval(1)
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expect(obj).to receive(:puts).with("#2")
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vcd.advance(1)
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expect(obj).to receive(:puts).with("0a")
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expect(obj).to receive(:puts).with("1c")
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a.setval(0)
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vcd.stop
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end
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end
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4
todo.txt
4
todo.txt
@ -1,2 +1,2 @@
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Must add tests for VCD and Device
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Parts of Port must get tests
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Must add tests for Device
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Must add tests for parts of Port
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26
tst.vcd
26
tst.vcd
@ -1,26 +0,0 @@
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$version
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RCircuit VCD Generator Version 0.0
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$end
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$date
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Thu Jul 12 07:57:29 2018
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$end
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$timescale 1ps $end
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$scope module TOP $end
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$var wire 8 a a[0:7] $end
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$var wire 8 b b[0:7] $end
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$upscope $end
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$enddefinitions $end
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$dumpvars
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b0 a
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b0 b
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$end
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#0
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b1000 a
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b1010 b
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#1
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b10000 a
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b11101 b
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#2
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b0 a
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b0 b
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#3
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27
vcd_test.rb
27
vcd_test.rb
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#xor_test.rb
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require_relative "lib/rcircuit/port.rb"
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require_relative "lib/rcircuit/gate.rb"
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require_relative "lib/rcircuit/xor.rb"
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require_relative "lib/rcircuit/vcd.rb"
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in_a = Port.new(1, "A")
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in_b = Port.new(1, "B")
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gate = XorGate.new(in_a, in_b)
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vcd = VCD.new("vcd_test.vcd").attach(in_a)
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.attach(in_b)
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.attach(gate.out, "OUT")
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in_a.setval(0)
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in_b.setval(0)
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vcd.start
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in_a.setval(1)
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vcd.advance(1000).write
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in_b.setval(1)
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vcd.advance(1000).write
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in_a.setval(0)
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vcd.advance(1000).write
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vcd.advance(1000)
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vcd.finish
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