Add VCD tets

This commit is contained in:
pjht 2018-07-15 17:14:31 -05:00
parent f2bc567ee7
commit f98142f387
5 changed files with 55 additions and 60 deletions

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@ -1,6 +1,9 @@
## Creates VCD files from port states
class VCD
# @!attribute [w] fd
# @api private
attr_writer :fd
# @param filename [String] The filename to output to
# @param timescale [String] The timescale
def initialize(filename, timescale="1ps")
@ -28,7 +31,12 @@ class VCD
write_port_state(portname)
end
@fd.puts "$end"
@fd.puts "\#0"
@fd.puts "#0"
@portmap.each do |name,port|
port.add_callback do |value|
write_port_state(name)
end
end
end
# Stop logging
@ -49,16 +57,13 @@ class VCD
@idmap[portname] = @id
@id=@id.next()
@portmap[portname] = port
port.add_callback do |value|
write_port_state(portname)
end
end
# Advance x timesteps
# @param timesteps [Integer] The number of timesteps to advance
def advance(timesteps)
@time += timesteps
@fd.puts "\##{@time.to_s}"
@fd.puts "##{@time.to_s}"
end
private

43
spec/vcd_spec.rb Normal file
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@ -0,0 +1,43 @@
describe VCD do
it "Outputs VCD files" do
a=Port.new(1)
b=Port.new(1)
gate=XorGate.new(a,b)
vcd=VCD.new("vcd_test.vcd")
obj=double()
allow(obj).to receive(:puts)
allow(obj).to receive(:close)
vcd.fd=obj
`rm vcd_test.vcd`
vcd.attach(a,"a")
vcd.attach(b,"b")
vcd.attach(gate.out, "out")
expect(obj).to receive(:puts).with("$scope module TOP $end")
expect(obj).to receive(:puts).with("$var wire 1 a a $end")
expect(obj).to receive(:puts).with("$var wire 1 b b $end")
expect(obj).to receive(:puts).with("$var wire 1 c out $end")
expect(obj).to receive(:puts).with("$upscope $end")
expect(obj).to receive(:puts).with("$enddefinitions $end")
expect(obj).to receive(:puts).with("$dumpvars")
expect(obj).to receive(:puts).with("0a")
expect(obj).to receive(:puts).with("0b")
expect(obj).to receive(:puts).with("0c")
expect(obj).to receive(:puts).with("$end")
expect(obj).to receive(:puts).with("#0")
vcd.start
expect(obj).to receive(:puts).with("1a")
expect(obj).to receive(:puts).with("1c")
a.setval(1)
expect(obj).to receive(:puts).with("#1")
vcd.advance(1)
expect(obj).to receive(:puts).with("1b")
expect(obj).to receive(:puts).with("0c")
b.setval(1)
expect(obj).to receive(:puts).with("#2")
vcd.advance(1)
expect(obj).to receive(:puts).with("0a")
expect(obj).to receive(:puts).with("1c")
a.setval(0)
vcd.stop
end
end

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@ -1,2 +1,2 @@
Must add tests for VCD and Device
Parts of Port must get tests
Must add tests for Device
Must add tests for parts of Port

26
tst.vcd
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@ -1,26 +0,0 @@
$version
RCircuit VCD Generator Version 0.0
$end
$date
Thu Jul 12 07:57:29 2018
$end
$timescale 1ps $end
$scope module TOP $end
$var wire 8 a a[0:7] $end
$var wire 8 b b[0:7] $end
$upscope $end
$enddefinitions $end
$dumpvars
b0 a
b0 b
$end
#0
b1000 a
b1010 b
#1
b10000 a
b11101 b
#2
b0 a
b0 b
#3

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@ -1,27 +0,0 @@
#xor_test.rb
require_relative "lib/rcircuit/port.rb"
require_relative "lib/rcircuit/gate.rb"
require_relative "lib/rcircuit/xor.rb"
require_relative "lib/rcircuit/vcd.rb"
in_a = Port.new(1, "A")
in_b = Port.new(1, "B")
gate = XorGate.new(in_a, in_b)
vcd = VCD.new("vcd_test.vcd").attach(in_a)
.attach(in_b)
.attach(gate.out, "OUT")
in_a.setval(0)
in_b.setval(0)
vcd.start
in_a.setval(1)
vcd.advance(1000).write
in_b.setval(1)
vcd.advance(1000).write
in_a.setval(0)
vcd.advance(1000).write
vcd.advance(1000)
vcd.finish