From 5b697571f9142689648271bb98731ab0e829c046 Mon Sep 17 00:00:00 2001
From: pjht <terppa05@gmail.com>
Date: Fri, 8 May 2020 07:17:08 -0500
Subject: [PATCH 1/4] Fix the NOT gate

---
 lib/rcircuit/not.rb | 9 +--------
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/lib/rcircuit/not.rb b/lib/rcircuit/not.rb
index 3eb23c8..c828f49 100644
--- a/lib/rcircuit/not.rb
+++ b/lib/rcircuit/not.rb
@@ -1,13 +1,6 @@
 # Represents a NOT gate
 class NotGate < Gate
 
-  # (see Gate#initialize)
-  def initialize(*args)
-    @outmask=0
-    super
-    @outmask=(2**@width)-1
-  end
-
   # Add a port to the gate. As this is a NOT gate, there may only be one port.
   # @param (see Gate#add_input)
   # @return [void]
@@ -22,6 +15,6 @@ class NotGate < Gate
   #  Calculates NOT of input and sets output port to that value.
   # @param vals [Array<Integer>] List of values for connected ports.
   def inputs_changed(vals)
-    out.setval((~vals[0]) & @outmask)
+    out.setval((~vals[0]) & ((2**@width)-1))
   end
 end

From d6f17b257329c6c607418735c496c851854371c3 Mon Sep 17 00:00:00 2001
From: pjht <terppa05@gmail.com>
Date: Fri, 8 May 2020 07:18:00 -0500
Subject: [PATCH 2/4] Add rspec to the Gemfile

---
 Gemfile      |  1 +
 Gemfile.lock | 17 ++++++++++++++++-
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/Gemfile b/Gemfile
index 00c7933..0468dba 100644
--- a/Gemfile
+++ b/Gemfile
@@ -1,3 +1,4 @@
 source "https://rubygems.org"
 gem "yard"
 gem "pry"
+gem "rspec"
diff --git a/Gemfile.lock b/Gemfile.lock
index eb0675d..634fbac 100644
--- a/Gemfile.lock
+++ b/Gemfile.lock
@@ -2,10 +2,24 @@ GEM
   remote: https://rubygems.org/
   specs:
     coderay (1.1.2)
+    diff-lcs (1.3)
     method_source (0.9.0)
     pry (0.11.3)
       coderay (~> 1.1.0)
       method_source (~> 0.9.0)
+    rspec (3.9.0)
+      rspec-core (~> 3.9.0)
+      rspec-expectations (~> 3.9.0)
+      rspec-mocks (~> 3.9.0)
+    rspec-core (3.9.2)
+      rspec-support (~> 3.9.3)
+    rspec-expectations (3.9.1)
+      diff-lcs (>= 1.2.0, < 2.0)
+      rspec-support (~> 3.9.0)
+    rspec-mocks (3.9.1)
+      diff-lcs (>= 1.2.0, < 2.0)
+      rspec-support (~> 3.9.0)
+    rspec-support (3.9.3)
     yard (0.9.14)
 
 PLATFORMS
@@ -13,7 +27,8 @@ PLATFORMS
 
 DEPENDENCIES
   pry
+  rspec
   yard
 
 BUNDLED WITH
-   1.16.1
+   1.17.2

From f83dfba2e0f3bf2def0aac826b4cd95f5fe240d5 Mon Sep 17 00:00:00 2001
From: pjht <terppa05@gmail.com>
Date: Fri, 8 May 2020 07:18:18 -0500
Subject: [PATCH 3/4] Add tests for gate input width checking

---
 spec/gate_spec.rb | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/spec/gate_spec.rb b/spec/gate_spec.rb
index 416071c..6e43a94 100644
--- a/spec/gate_spec.rb
+++ b/spec/gate_spec.rb
@@ -10,6 +10,21 @@ describe Gate do
       end
     end
   end
+  
+  it "makes sure that all ports have the same width on creation" do
+    a=Port.new(8)
+    b=Port.new(7)
+    expect{klass.new(a,b)}.to raise_error ArgumentError,"Incorrect width 7, expected 8"
+  end
+  
+  it "makes sure that all ports have the same width on adding a port" do
+    a=Port.new(8)
+    b=Port.new(8)
+    gate=klass.new(a,b)
+    port=Port.new(7)
+    expect{gate.add_input(port)}.to raise_error ArgumentError,"Incorrect width 7, expected 8"
+  end
+  
   it "calls #inputs_changed when input values change or an input is added" do
     a=Port.new(8)
     b=Port.new(8)

From ed97d1e5c3edcae69d71edc15f83567e7cd04a09 Mon Sep 17 00:00:00 2001
From: pjht <terppa05@gmail.com>
Date: Fri, 8 May 2020 07:45:01 -0500
Subject: [PATCH 4/4] Documentation work

---
 lib/rcircuit/gate.rb | 1 +
 lib/rcircuit/vcd.rb  | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/lib/rcircuit/gate.rb b/lib/rcircuit/gate.rb
index e1bc01f..9124f91 100644
--- a/lib/rcircuit/gate.rb
+++ b/lib/rcircuit/gate.rb
@@ -43,6 +43,7 @@ class Gate
   # @param table [Array<Array<Integer>>] The truth table,
   #   which is an array of entries. The last value in the entry is the expected output,
   #   the rest are the inputs to the ports.
+  # @return [Boolean] Whether the truth table matches the gate's behavior
   def self.test_table(table)
     ports=[]
     (table[0].length-1).times do
diff --git a/lib/rcircuit/vcd.rb b/lib/rcircuit/vcd.rb
index aaf6989..eaaa04c 100644
--- a/lib/rcircuit/vcd.rb
+++ b/lib/rcircuit/vcd.rb
@@ -2,7 +2,8 @@
 class VCD
 
   # @!attribute [w] fd
-  #   @api private
+  # @api private
+  # Used for testing to set the file to an RSpec double.
   attr_writer :fd
   # @param filename [String] The filename to output to
   # @param timescale [String] The timescale