183 lines
6.9 KiB
C
183 lines
6.9 KiB
C
/**
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* \file
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*/
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#include <stdint.h>
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#include <string.h>
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#define NUM_ENTRIES 6 //!< Number of entries in the GDT
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extern uint32_t int_stack_top; //!< Initial kernel stack before the kernel's first yield
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/**
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* Represents an entry in the GDT.
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*/
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typedef struct {
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uint16_t limit_low16;//!< Low 16 bits of the limit
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uint16_t base_low16; //!< Low 16 bits of the base
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uint8_t base_mid8; //!< Middle 8 bits of the base
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uint8_t access; /**<
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Access byte. Gives info about the descriptor. <br>
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Format: <br>
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Bit 7: Present. Must be 1 for all valid selectors. <br>
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Bits 6-5. Privilege. Contains the ring level for the selector. 0 for kernel mode, 3 for user mode. <br>
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Bit 4. Descriptor type. Must be set for code/data segments and cleared for system segments like the TSS. <br>
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Bit 3. Executable. If this bit is set, it is a code selector, otherwise a data selector. <br>
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Bit 2. Direction/Conforming. Too complex to explain, should be set to 0. <br>
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Bit 1. Readable/Writable. For code sels, this bit sets whther you can use it like a read-only data segment. For data sels, it sets whether the selector is writable. <br>
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Bit 0. Acessed bit. Set to 0. <br>
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*/
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uint8_t limit_flags; /**<
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High nibble of this contains two flags, and the lower niblle contains the high 4 bits of the limit. <br>
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The flags are: <br>
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Bit 3. Granularity. 0 for byte granularity, 1 for 4 KB granularity. <br>
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Bit 2. Size. 0 for 16 bit protected mode, 1 for 32 bit protected mode. <br>
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Bits 1-0. Unused. Set to 0. <br>
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*/
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uint8_t base_high8; //!< High 8 bits of the base
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} __attribute__((packed)) gdt_entry;
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/**
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* Pointed to by the GDTR to tell the processor the GDT's size and address.
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*/
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typedef struct {
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uint16_t size; //!< Size of the GDT.
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gdt_entry* address; //!< Address of the GDT.
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} __attribute__((packed)) gdt_description;
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/**
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* Represents a TSS.
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*/
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typedef struct {
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uint32_t prev_tss; //!< The previous TSS - if we used hardware task switching this would form a linked list.
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uint32_t esp0; //!< The stack pointer to load when we change to kernel mode.
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uint32_t ss0; //!< The stack segment to load when we change to kernel mode.
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uint32_t esp1; //!< Unused
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uint32_t ss1; //!< Unused
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uint32_t ss2; //!< Unused
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uint32_t esp2; //!< Unused
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uint32_t cr3; //!< Unused
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uint32_t eip; //!< Unused
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uint32_t eflags; //!< Unused
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uint32_t eax; //!< Unused
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uint32_t ecx; //!< Unused
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uint32_t edx; //!< Unused
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uint32_t ebx; //!< Unused
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uint32_t esp; //!< Unused
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uint32_t ebp; //!< Unused
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uint32_t esi; //!< Unused
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uint32_t edi; //!< Unused
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uint32_t es; //!< The value to load into ES when we change to kernel mode.
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uint32_t cs; //!< The value to load into CS when we change to kernel mode.
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uint32_t ss; //!< The value to load into SS when we change to kernel mode.
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uint32_t ds; //!< The value to load into DS when we change to kernel mode.
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uint32_t fs; //!< The value to load into FS when we change to kernel mode.
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uint32_t gs; //!< The value to load into GS when we change to kernel mode.
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uint32_t ldt; //!< Unused
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uint16_t trap; //!< Unused
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uint16_t iomap_base; //!< Offset of the IOPB in the TSS.
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char iopb[8192]; //!< IO port bitmap
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uint8_t set_ff; //!< Must be set to 0xFF to mark the end of the IOPB
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} __attribute__((packed)) tss_entry;
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static gdt_entry gdt[NUM_ENTRIES]; //!< The GDT
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static gdt_description gdt_desc; //!< The value to load into the GDTR
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tss_entry tss; //!< The TSS
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/**
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* Set a GDT entry.
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* \param i The GDT entry to set.
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* \param base The base of the GDT entry.
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* \param limit The limit of the GDT entry.
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* \param access The access byte of the GDT entry.
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*/
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static void set_entry(int i,uint32_t base,uint32_t limit,uint8_t access) {
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gdt[i].limit_low16=limit&0xFFFF;
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gdt[i].base_low16=base&0xFFFFF;
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gdt[i].base_mid8=(base&0xFF0000)>>16;
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gdt[i].access=access;
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uint8_t limit_high4=(limit&0xF0000)>>16;
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gdt[i].limit_flags=0xC0|limit_high4;
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gdt[i].base_high8=(base&0xFF000000)>>24;
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}
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/**
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* Set a GDT entry.
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* \param num The GDT entry to set.
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* \param ss0 The kernel stack selector.
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* \param esp0 The kernel stack pointer.
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*/
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static void write_tss(int32_t num, uint16_t ss0, uint32_t esp0) {
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// Firstly, let's compute the base and limit of our entry into the GDT.
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uint32_t base = (uint32_t) &tss;
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uint32_t limit = base + sizeof(tss_entry);
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// Now, add our TSS descriptor's address to the GDT.
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gdt[num].limit_low16=limit&0xFFFF;
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gdt[num].base_low16=base&0xFFFFF;
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gdt[num].base_mid8=(base&0xFF0000)>>16;
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gdt[num].access=0xe9;
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gdt[num].limit_flags=(limit&0xF0000)>>16;
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gdt[num].base_high8=(base&0xFF000000)>>24;
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// Ensure the descriptor is initially zero.
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memset((void*)&tss,0,sizeof(tss));
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tss.ss0 = ss0; // Set the kernel stack segment.
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tss.esp0 = esp0; // Set the kernel stack pointer.
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//Set the last byte to 0xFF (End marker for IOPB)
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tss.set_ff=0xFF;
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// Now, set the offset for the IOPB
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// (All ports are already OK from the zeroing)
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tss.iomap_base=104;
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// Here we set the cs, ss, ds, es, fs and gs entries in the TSS. These specify what
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// segments should be loaded when the processor switches to kernel mode. Therefore
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// they are just our normal kernel code/data segments - 0x08 and 0x10 respectively,
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// but with the last two bits set, making 0x0b and 0x13. The setting of these bits
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// sets the RPL (requested privilege level) to 3, meaning that this TSS can be used
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// to switch to kernel mode from ring 3.
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tss.cs = 0x0b;
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tss.ss = tss.ds = tss.es = tss.fs = tss.gs = 0x13;
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}
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void allow_all_ports() {
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for (int i=0;i<8192;i++) {
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tss.iopb[i]=0;
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}
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}
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void block_all_ports() {
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for (int i=0;i<8192;i++) {
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tss.iopb[i]=0xFF;
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}
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}
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void gdt_init() {
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set_entry(0,0,0,0);
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set_entry(1,0,0xFFFFF,0b10011010);
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set_entry(2,0,0xFFFFF,0b10010010);
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set_entry(3,0,0xFFFFF,0b11111010);
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set_entry(4,0,0xFFFFF,0b11110010);
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write_tss(5,0x10,int_stack_top+0xC0000000);
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gdt_desc.size=(sizeof(gdt_entry)*NUM_ENTRIES)-1;
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gdt_desc.address=gdt;
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asm volatile(" \
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lgdt (%%eax); \
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jmp $0x8,$gdt_init_asm_code_upd; \
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gdt_init_asm_code_upd: \
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mov $0x10, %%ax; \
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mov %%ax, %%ds; \
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mov %%ax, %%ss; \
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mov %%ax, %%es; \
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mov %%ax, %%fs; \
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mov %%ax, %%gs; \
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"::"a"((uint32_t)&gdt_desc));
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asm volatile("mov $0x2B, %ax; \
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ltr %ax; \
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");
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}
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