logisim update
This commit is contained in:
pjht
parent
b1ab59bc79
commit
cfa790b35f
208
8080.circ
208
8080.circ
@ -1,7 +1,34 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="2.7.1" version="1.0">
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This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<lib desc="#Wiring" name="0"/>
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<lib desc="#Wiring" name="0">
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<tool name="Splitter">
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<a name="fanout" val="7"/>
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<a name="incoming" val="7"/>
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<a name="appear" val="right"/>
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</tool>
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<tool name="Pin">
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<a name="tristate" val="false"/>
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<a name="pull" val="down"/>
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<a name="label" val="Reset"/>
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</tool>
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<tool name="Probe">
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<a name="facing" val="west"/>
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<a name="radix" val="16"/>
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</tool>
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<tool name="Tunnel">
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<a name="label" val="JMP"/>
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</tool>
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<tool name="Pull Resistor">
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<a name="facing" val="north"/>
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</tool>
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<tool name="Clock">
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<a name="facing" val="north"/>
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</tool>
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<tool name="Constant">
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<a name="value" val="0x0"/>
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</tool>
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</lib>
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<lib desc="#Gates" name="1">
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<tool name="AND Gate">
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<a name="inputs" val="8"/>
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@ -33,8 +60,8 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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</options>
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<mappings>
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<tool lib="6" map="Button2" name="Menu Tool"/>
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<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
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<tool lib="6" map="Button3" name="Menu Tool"/>
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<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="6" name="Poke Tool"/>
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@ -65,8 +92,8 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<wire from="(410,730)" to="(430,730)"/>
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<wire from="(280,500)" to="(390,500)"/>
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<wire from="(420,500)" to="(600,500)"/>
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<wire from="(380,510)" to="(390,510)"/>
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<wire from="(370,390)" to="(400,390)"/>
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<wire from="(380,510)" to="(390,510)"/>
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<wire from="(400,520)" to="(400,530)"/>
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<wire from="(340,440)" to="(340,620)"/>
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<wire from="(280,720)" to="(390,720)"/>
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@ -86,15 +113,15 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<wire from="(410,520)" to="(430,520)"/>
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<wire from="(370,460)" to="(370,530)"/>
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<wire from="(290,290)" to="(290,440)"/>
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<wire from="(280,600)" to="(310,600)"/>
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<wire from="(280,480)" to="(330,480)"/>
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<wire from="(280,600)" to="(310,600)"/>
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<wire from="(360,580)" to="(360,660)"/>
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<wire from="(280,640)" to="(350,640)"/>
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<wire from="(410,660)" to="(430,660)"/>
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<wire from="(400,380)" to="(400,390)"/>
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<wire from="(480,560)" to="(600,560)"/>
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<wire from="(410,730)" to="(410,760)"/>
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<wire from="(420,640)" to="(460,640)"/>
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<wire from="(410,730)" to="(410,760)"/>
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<wire from="(430,520)" to="(430,590)"/>
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<wire from="(480,560)" to="(480,710)"/>
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<wire from="(280,510)" to="(360,510)"/>
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@ -102,13 +129,13 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<wire from="(330,430)" to="(390,430)"/>
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<wire from="(370,530)" to="(370,600)"/>
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<wire from="(410,380)" to="(430,380)"/>
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<wire from="(380,610)" to="(380,640)"/>
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<wire from="(400,730)" to="(400,740)"/>
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<wire from="(380,610)" to="(380,640)"/>
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<wire from="(320,360)" to="(320,460)"/>
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<wire from="(370,600)" to="(400,600)"/>
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<wire from="(430,590)" to="(430,660)"/>
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<wire from="(300,300)" to="(390,300)"/>
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<wire from="(430,450)" to="(430,520)"/>
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<wire from="(300,300)" to="(390,300)"/>
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<wire from="(370,460)" to="(400,460)"/>
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<wire from="(400,590)" to="(400,600)"/>
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<wire from="(330,540)" to="(330,610)"/>
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@ -159,29 +186,17 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<wire from="(450,520)" to="(600,520)"/>
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<wire from="(370,320)" to="(370,390)"/>
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<wire from="(350,490)" to="(350,640)"/>
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<comp lib="0" loc="(280,540)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="H in"/>
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</comp>
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<comp lib="0" loc="(280,500)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="D in"/>
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</comp>
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<comp lib="0" loc="(280,580)" name="Pin">
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<a name="label" val="en A"/>
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</comp>
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<comp lib="4" loc="(420,290)" name="Register"/>
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<comp lib="4" loc="(420,360)" name="Register"/>
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<comp lib="0" loc="(600,560)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<comp lib="0" loc="(280,440)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="L in"/>
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<a name="labelloc" val="east"/>
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<a name="label" val="A in"/>
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</comp>
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<comp lib="4" loc="(420,710)" name="Register"/>
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<comp lib="0" loc="(600,540)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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@ -190,62 +205,6 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<a name="label" val="H in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(280,480)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="C in"/>
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</comp>
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<comp lib="0" loc="(280,640)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en D"/>
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</comp>
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<comp lib="4" loc="(420,430)" name="Register"/>
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<comp lib="0" loc="(280,520)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="E in"/>
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</comp>
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<comp lib="0" loc="(280,660)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en E"/>
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</comp>
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<comp lib="4" loc="(420,710)" name="Register"/>
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<comp lib="4" loc="(420,500)" name="Register"/>
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<comp lib="0" loc="(600,440)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="A in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(280,460)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="B in"/>
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</comp>
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<comp lib="0" loc="(280,560)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="L in"/>
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</comp>
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<comp lib="0" loc="(600,480)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="C in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(370,760)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="res"/>
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</comp>
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<comp lib="0" loc="(280,440)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="A in"/>
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</comp>
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<comp lib="0" loc="(600,460)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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@ -254,16 +213,45 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<a name="label" val="B in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="4" loc="(420,570)" name="Register"/>
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<comp lib="0" loc="(280,680)" name="Pin">
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<comp lib="0" loc="(280,520)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="en H"/>
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<a name="label" val="E in"/>
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</comp>
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<comp lib="4" loc="(420,430)" name="Register"/>
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<comp lib="0" loc="(280,700)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en L"/>
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</comp>
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<comp lib="4" loc="(420,500)" name="Register"/>
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<comp lib="4" loc="(420,360)" name="Register"/>
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<comp lib="4" loc="(420,290)" name="Register"/>
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<comp lib="0" loc="(600,480)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="C in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(280,660)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en E"/>
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</comp>
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<comp lib="4" loc="(420,640)" name="Register"/>
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<comp lib="0" loc="(280,620)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en C"/>
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</comp>
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<comp lib="0" loc="(280,480)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="C in"/>
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</comp>
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<comp lib="0" loc="(280,540)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="H in"/>
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</comp>
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<comp lib="0" loc="(600,500)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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@ -272,11 +260,54 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<a name="label" val="D in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(280,700)" name="Pin">
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<comp lib="0" loc="(280,560)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="en L"/>
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<a name="label" val="L in"/>
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</comp>
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<comp lib="0" loc="(280,580)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en A"/>
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</comp>
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<comp lib="0" loc="(280,600)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en B"/>
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</comp>
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<comp lib="0" loc="(600,440)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="A in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(600,560)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="L in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(370,740)" name="Clock"/>
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<comp lib="0" loc="(370,760)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="res"/>
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</comp>
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<comp lib="0" loc="(280,460)" name="Pin">
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<a name="width" val="8"/>
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<a name="tristate" val="false"/>
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<a name="label" val="B in"/>
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</comp>
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<comp lib="0" loc="(280,680)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en H"/>
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</comp>
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<comp lib="0" loc="(280,640)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en D"/>
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</comp>
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<comp lib="4" loc="(420,640)" name="Register"/>
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<comp lib="0" loc="(600,520)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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@ -285,10 +316,7 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<a name="label" val="E in"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(280,600)" name="Pin">
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<a name="tristate" val="false"/>
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<a name="label" val="en B"/>
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</comp>
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<comp lib="4" loc="(420,570)" name="Register"/>
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</circuit>
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<circuit name="ALU">
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<a name="circuit" val="ALU"/>
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@ -297,16 +325,16 @@ This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<a name="clabelfont" val="SansSerif plain 12"/>
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<wire from="(350,160)" to="(350,250)"/>
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<wire from="(340,220)" to="(340,260)"/>
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<wire from="(340,260)" to="(350,260)"/>
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<wire from="(180,220)" to="(340,220)"/>
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<wire from="(340,260)" to="(350,260)"/>
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<wire from="(180,160)" to="(350,160)"/>
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<comp lib="3" loc="(180,220)" name="Subtractor"/>
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<comp lib="2" loc="(390,290)" name="Multiplexer">
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<a name="select" val="3"/>
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<a name="width" val="8"/>
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<a name="disabled" val="0"/>
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<a name="enable" val="false"/>
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</comp>
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<comp lib="3" loc="(180,220)" name="Subtractor"/>
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<comp lib="3" loc="(180,160)" name="Adder"/>
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</circuit>
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</project>
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1468
TK16X3.circ
1468
TK16X3.circ
File diff suppressed because it is too large
Load Diff
@ -1,12 +0,0 @@
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0 = lda
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1 = ldb
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2 = ldai
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3 = ldbi
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4 = add
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5 = sub
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6 = mult
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7 = div
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8 = sta
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9 = stb
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a = str
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b = jmp
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13
guide
13
guide
@ -1,13 +0,0 @@
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help:
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Inputs:
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Takeover: the way you switch control of the the buses to you.
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addr code: the code ram address.
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code: the code that it executes, The first 4 hex digits are the address, the remaining 2 are the code, there is a instruction set to the right of this input.
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writec: write the current code.
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addr data: the data ram address
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data in: the data to write
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writed: write the current data.
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execute: executes the program.
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Probes:
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acc: shows the accumulator.
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do: data out of the ram.
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249
turing.circ
Normal file
249
turing.circ
Normal file
@ -0,0 +1,249 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="2.7.1" version="1.0">
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This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<lib desc="#Wiring" name="0"/>
|
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<lib desc="#Gates" name="1"/>
|
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<lib desc="#Plexers" name="2">
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<tool name="Demultiplexer">
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<a name="select" val="2"/>
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</tool>
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<tool name="Decoder">
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<a name="select" val="2"/>
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</tool>
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</lib>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4">
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<tool name="Counter">
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<a name="width" val="2"/>
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<a name="max" val="0x2"/>
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</tool>
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<tool name="ROM">
|
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<a name="contents">addr/data: 8 8
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0
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</a>
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</tool>
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</lib>
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<lib desc="#I/O" name="5"/>
|
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<lib desc="#Base" name="6">
|
||||
<tool name="Text Tool">
|
||||
<a name="text" val=""/>
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||||
<a name="font" val="SansSerif plain 12"/>
|
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<a name="halign" val="center"/>
|
||||
<a name="valign" val="base"/>
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</tool>
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</lib>
|
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<main name="main"/>
|
||||
<options>
|
||||
<a name="gateUndefined" val="ignore"/>
|
||||
<a name="simlimit" val="50000"/>
|
||||
<a name="simrand" val="0"/>
|
||||
</options>
|
||||
<mappings>
|
||||
<tool lib="6" map="Button2" name="Menu Tool"/>
|
||||
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
|
||||
<tool lib="6" map="Button3" name="Menu Tool"/>
|
||||
</mappings>
|
||||
<toolbar>
|
||||
<tool lib="6" name="Poke Tool"/>
|
||||
<tool lib="6" name="Edit Tool"/>
|
||||
<tool lib="6" name="Text Tool">
|
||||
<a name="text" val=""/>
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
<a name="halign" val="center"/>
|
||||
<a name="valign" val="base"/>
|
||||
</tool>
|
||||
<sep/>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="en"/>
|
||||
</tool>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
<a name="labelloc" val="east"/>
|
||||
</tool>
|
||||
<tool lib="1" name="NOT Gate"/>
|
||||
<tool lib="1" name="AND Gate">
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
</tool>
|
||||
<tool lib="1" name="OR Gate">
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
</tool>
|
||||
</toolbar>
|
||||
<circuit name="main">
|
||||
<a name="circuit" val="main"/>
|
||||
<a name="clabel" val=""/>
|
||||
<a name="clabelup" val="east"/>
|
||||
<a name="clabelfont" val="SansSerif plain 12"/>
|
||||
<wire from="(1350,450)" to="(1350,710)"/>
|
||||
<wire from="(1480,640)" to="(1510,640)"/>
|
||||
<wire from="(1350,710)" to="(1370,710)"/>
|
||||
<wire from="(1530,520)" to="(1530,600)"/>
|
||||
<wire from="(230,460)" to="(250,460)"/>
|
||||
<wire from="(360,450)" to="(530,450)"/>
|
||||
<wire from="(1000,600)" to="(1380,600)"/>
|
||||
<wire from="(1380,560)" to="(1470,560)"/>
|
||||
<wire from="(1490,430)" to="(1500,430)"/>
|
||||
<wire from="(1210,780)" to="(1460,780)"/>
|
||||
<wire from="(950,680)" to="(1000,680)"/>
|
||||
<wire from="(1480,660)" to="(1490,660)"/>
|
||||
<wire from="(1130,820)" to="(1190,820)"/>
|
||||
<wire from="(950,680)" to="(950,870)"/>
|
||||
<wire from="(520,390)" to="(520,640)"/>
|
||||
<wire from="(1180,800)" to="(1190,800)"/>
|
||||
<wire from="(1380,500)" to="(1380,560)"/>
|
||||
<wire from="(530,390)" to="(540,390)"/>
|
||||
<wire from="(860,560)" to="(1090,560)"/>
|
||||
<wire from="(860,390)" to="(860,520)"/>
|
||||
<wire from="(770,470)" to="(1030,470)"/>
|
||||
<wire from="(530,390)" to="(530,450)"/>
|
||||
<wire from="(1370,620)" to="(1490,620)"/>
|
||||
<wire from="(100,450)" to="(200,450)"/>
|
||||
<wire from="(1530,600)" to="(1540,600)"/>
|
||||
<wire from="(1400,700)" to="(1450,700)"/>
|
||||
<wire from="(260,470)" to="(260,820)"/>
|
||||
<wire from="(1150,500)" to="(1380,500)"/>
|
||||
<wire from="(510,390)" to="(520,390)"/>
|
||||
<wire from="(1320,400)" to="(1380,400)"/>
|
||||
<wire from="(1010,690)" to="(1010,820)"/>
|
||||
<wire from="(1540,600)" to="(1540,650)"/>
|
||||
<wire from="(1170,520)" to="(1170,530)"/>
|
||||
<wire from="(1470,560)" to="(1470,590)"/>
|
||||
<wire from="(520,640)" to="(960,640)"/>
|
||||
<wire from="(1510,590)" to="(1510,640)"/>
|
||||
<wire from="(860,560)" to="(860,600)"/>
|
||||
<wire from="(900,610)" to="(900,820)"/>
|
||||
<wire from="(960,610)" to="(960,640)"/>
|
||||
<wire from="(1470,590)" to="(1510,590)"/>
|
||||
<wire from="(1450,680)" to="(1450,700)"/>
|
||||
<wire from="(740,710)" to="(1350,710)"/>
|
||||
<wire from="(1350,450)" to="(1510,450)"/>
|
||||
<wire from="(700,450)" to="(870,450)"/>
|
||||
<wire from="(680,390)" to="(690,390)"/>
|
||||
<wire from="(860,600)" to="(890,600)"/>
|
||||
<wire from="(950,870)" to="(1490,870)"/>
|
||||
<wire from="(1220,410)" to="(1280,410)"/>
|
||||
<wire from="(1090,560)" to="(1300,560)"/>
|
||||
<wire from="(1370,620)" to="(1370,690)"/>
|
||||
<wire from="(1480,650)" to="(1540,650)"/>
|
||||
<wire from="(1380,590)" to="(1380,600)"/>
|
||||
<wire from="(1090,450)" to="(1090,560)"/>
|
||||
<wire from="(1040,410)" to="(1060,410)"/>
|
||||
<wire from="(1130,430)" to="(1130,820)"/>
|
||||
<wire from="(870,390)" to="(880,390)"/>
|
||||
<wire from="(1490,430)" to="(1490,620)"/>
|
||||
<wire from="(850,390)" to="(860,390)"/>
|
||||
<wire from="(1030,670)" to="(1050,670)"/>
|
||||
<wire from="(1150,430)" to="(1150,500)"/>
|
||||
<wire from="(530,450)" to="(700,450)"/>
|
||||
<wire from="(860,520)" to="(1040,520)"/>
|
||||
<wire from="(200,890)" to="(1570,890)"/>
|
||||
<wire from="(870,390)" to="(870,450)"/>
|
||||
<wire from="(1380,400)" to="(1380,420)"/>
|
||||
<wire from="(280,450)" to="(360,450)"/>
|
||||
<wire from="(1460,680)" to="(1460,780)"/>
|
||||
<wire from="(1090,450)" to="(1110,450)"/>
|
||||
<wire from="(770,470)" to="(770,590)"/>
|
||||
<wire from="(1040,410)" to="(1040,520)"/>
|
||||
<wire from="(1380,420)" to="(1460,420)"/>
|
||||
<wire from="(1010,820)" to="(1130,820)"/>
|
||||
<wire from="(900,820)" to="(1010,820)"/>
|
||||
<wire from="(360,390)" to="(370,390)"/>
|
||||
<wire from="(260,820)" to="(900,820)"/>
|
||||
<wire from="(1300,520)" to="(1300,560)"/>
|
||||
<wire from="(1380,590)" to="(1460,590)"/>
|
||||
<wire from="(1030,390)" to="(1030,470)"/>
|
||||
<wire from="(1490,660)" to="(1490,870)"/>
|
||||
<wire from="(920,590)" to="(960,590)"/>
|
||||
<wire from="(690,530)" to="(1170,530)"/>
|
||||
<wire from="(1300,520)" to="(1530,520)"/>
|
||||
<wire from="(1090,430)" to="(1090,450)"/>
|
||||
<wire from="(770,590)" to="(890,590)"/>
|
||||
<wire from="(1200,390)" to="(1280,390)"/>
|
||||
<wire from="(1050,390)" to="(1050,670)"/>
|
||||
<wire from="(100,450)" to="(100,870)"/>
|
||||
<wire from="(100,870)" to="(950,870)"/>
|
||||
<wire from="(1460,440)" to="(1460,590)"/>
|
||||
<wire from="(1570,440)" to="(1570,890)"/>
|
||||
<wire from="(1190,800)" to="(1190,820)"/>
|
||||
<wire from="(690,390)" to="(690,530)"/>
|
||||
<wire from="(360,390)" to="(360,450)"/>
|
||||
<wire from="(700,390)" to="(700,450)"/>
|
||||
<wire from="(1020,390)" to="(1030,390)"/>
|
||||
<wire from="(700,390)" to="(710,390)"/>
|
||||
<wire from="(1050,390)" to="(1060,390)"/>
|
||||
<wire from="(200,470)" to="(200,890)"/>
|
||||
<wire from="(1220,410)" to="(1220,520)"/>
|
||||
<wire from="(1180,790)" to="(1180,800)"/>
|
||||
<wire from="(1170,520)" to="(1220,520)"/>
|
||||
<wire from="(1540,440)" to="(1570,440)"/>
|
||||
<comp lib="4" loc="(850,390)" name="RAM"/>
|
||||
<comp lib="2" loc="(1460,680)" name="Decoder">
|
||||
<a name="select" val="2"/>
|
||||
<a name="disabled" val="0"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(1020,390)" name="ROM">
|
||||
<a name="contents">addr/data: 8 8
|
||||
0
|
||||
</a>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1490,430)" name="AND Gate">
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(740,710)" name="Pin">
|
||||
<a name="tristate" val="false"/>
|
||||
<a name="label" val="en"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(941,328)" name="Text">
|
||||
<a name="text" val="new state"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(230,460)" name="OR Gate">
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(765,323)" name="Text">
|
||||
<a name="text" val="new sym"/>
|
||||
</comp>
|
||||
<comp lib="3" loc="(1000,600)" name="Comparator"/>
|
||||
<comp lib="1" loc="(1400,700)" name="AND Gate">
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
</comp>
|
||||
<comp lib="6" loc="(434,320)" name="Text">
|
||||
<a name="text" val="req state"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(280,450)" name="Counter"/>
|
||||
<comp lib="3" loc="(1320,400)" name="Comparator"/>
|
||||
<comp lib="4" loc="(680,390)" name="ROM">
|
||||
<a name="contents">addr/data: 8 8
|
||||
0
|
||||
</a>
|
||||
</comp>
|
||||
<comp lib="4" loc="(1200,390)" name="RAM">
|
||||
<a name="bus" val="separate"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(1210,780)" name="Counter">
|
||||
<a name="width" val="2"/>
|
||||
<a name="max" val="0x2"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(920,590)" name="Register"/>
|
||||
<comp lib="6" loc="(599,317)" name="Text">
|
||||
<a name="text" val="req sym"/>
|
||||
</comp>
|
||||
<comp lib="0" loc="(260,820)" name="Clock"/>
|
||||
<comp lib="1" loc="(1540,440)" name="AND Gate">
|
||||
<a name="size" val="30"/>
|
||||
<a name="inputs" val="2"/>
|
||||
<a name="negate0" val="true"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(1030,670)" name="Counter"/>
|
||||
<comp lib="4" loc="(510,390)" name="ROM">
|
||||
<a name="contents">addr/data: 8 8
|
||||
0 1
|
||||
</a>
|
||||
</comp>
|
||||
</circuit>
|
||||
</project>
|
||||
Loading…
Reference in New Issue
Block a user