248 lines
8.2 KiB
C
248 lines
8.2 KiB
C
/* Copyright (c) 2008, 2017 Stephen Checkoway
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/*! \file
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*
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* Functions for decoding and disassembling z80 instructions.
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* \author Stephen Checkoway
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* \version 0.1
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* \date 2008, 2017
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*/
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#ifndef ZEL_Z80_INSTRUCTIONS_H
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#define ZEL_Z80_INSTRUCTIONS_H
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#define _GNU_SOURCE
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#include <sys/types.h>
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#include <sys/param.h>
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#include <stdlib.h>
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#else
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#include <stdbool.h>
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#endif
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#include <zel/z80_instruction_types.h>
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/*! The type of a z80 instruction. Many z80 instructions are similar
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* and share a common type. For example, <code>add a,b</code> and
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* <code>add a,c</code> have the same type.
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*
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* The type of each instruction can be decoded as follows. Given an
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* instruction \c FOO_BAR_BAZ, \c FOO is the mnemonic, \c BAR is the
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* type of the first operand and \c BAZ is the type of the second. The
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* operand types are as follows:
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* - \c N 8 bit immediate
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* - \c NN 16 bit immediate
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* - \c I 8 bit signed displacement from an index register
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* - \c R 8 bit register
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* - \c RR 16 bit paired register
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* - \c MRR 16 bit paired register used as an address
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* - \c MNN 16 bit immediate used as an address
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*/
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#ifndef BYTE_ORDER
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#error define BYTE_ORDER
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#endif
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#if BYTE_ORDER == BIG_ENDIAN
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/*! Register values for the 8 bit registers which comprise the 16 bit
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* paired registers.
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*/
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enum
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{
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REG_B, //!< z80 register b.
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REG_C, //!< z80 register c.
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REG_D, //!< z80 register d.
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REG_E, //!< z80 register e.
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REG_H, //!< z80 register h.
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REG_L, //!< z80 register l.
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REG_A, //!< z80 register a.
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REG_F, //!< z80 register f.
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REG_IXH, //!< z80 register ixh.
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REG_IXL, //!< z80 register ixl.
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REG_IYH, //!< z80 register iyh.
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REG_IYL, //!< z80 register iyl.
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REG_PCH, //!< z80 register pch.
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REG_PCL, //!< z80 register pcl.
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/* No REG_SPH */
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/* No REG_SPL */
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/* No REG_BP */
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/* No REG_CP */
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/* No REG_DP */
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/* No REG_EP */
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/* No REG_HP */
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/* No REG_LP */
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/* No REG_AP */
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/* No REG_FP */
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REG_I = 24, //!< z80 register I. Interrupt page address register.
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REG_R, //!< z80 register r. Memory refresh register.
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INV = 0xff, //!< Invalid.
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};
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#elif BYTE_ORDER == LITTLE_ENDIAN
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/*! Register values for the 8 bit registers which comprise the 16 bit
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* paired registers.
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*/
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enum
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{
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REG_C, //!< z80 register c.
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REG_B, //!< z80 register b.
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REG_E, //!< z80 register e.
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REG_D, //!< z80 register d.
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REG_L, //!< z80 register l.
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REG_H, //!< z80 register h.
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REG_F, //!< z80 register f.
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REG_A, //!< z80 register a.
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REG_IXL, //!< z80 register ixl.
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REG_IXH, //!< z80 register ixh.
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REG_IYL, //!< z80 register iyl.
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REG_IYH, //!< z80 register iyh.
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REG_PCL, //!< z80 register pcl.
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REG_PCH, //!< z80 register pch.
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/* No single byte regs */
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REG_R = 24, //!< z80 register r. Memory refresh register.
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REG_I, //!< z80 register I. Interrupt page address register.
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INV = 0xff, //!< Invalid.
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};
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#else
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#error What endianness are you using?
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#endif
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/*! Condition flag bits as stored in register \c f.
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* The flags \c x and \c y are listed as unspecified by the z80 CPU
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* User's Manual but they are modified by a number of instructions.
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*/
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enum
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{
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FLAG_C, //!< Carry flag.
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FLAG_N, //!< Add/subtract flag.
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FLAG_P, //!< Parity/overflow flag (P/V).
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FLAG_X, //!< Flag 3.
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FLAG_H, //!< Half-carry flag.
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FLAG_Y, //!< Flag 5.
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FLAG_Z, //!< Zero flag.
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FLAG_S, //!< Sign flag.
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};
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/*! Condition flags. The condition is met if the corresponding flag is
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* set appropriately.
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*/
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enum
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{
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COND_NZ = -FLAG_Z-1, //!< Flag Z is reset.
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COND_Z = FLAG_Z, //!< Flag Z is set.
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COND_NC = -FLAG_C-1, //!< Flag C is reset.
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COND_C = FLAG_C, //!< Flag C is set.
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COND_PO = -FLAG_P-1, //!< Flag P/V is reset.
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COND_PE = FLAG_P, //!< Flag P/V is set.
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COND_P = -FLAG_S-1, //!< Flag S is reset.
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COND_M = FLAG_S, //!< Flag S is set.
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};
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/* Exactly two instructions contain both an offset and an immediate:
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* dd36 d n: ld (ix+d),n
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* fd36 d n: ld (iy+d),n */
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/*! Describes the layout of the operands for an instruction. */
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enum
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{
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TYPE_NONE, //!< No operands.
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TYPE_IMM_N, //!< 8 bit immediate.
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TYPE_IMM_NN, //!< 16 bit immediate.
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TYPE_OFFSET, //!< 8 bit signed offset.
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TYPE_DISP, //!< 8 bit signed offset - 2.
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TYPE_OFFSET_IMM_N, //!< 8 bit signed offset and 8 bit immediate.
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};
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// 4 (3) words native sized words on 32 (64) bit machine.
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/*! Uniform template for the instruction tables.
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* \headerfile z80_instructions.h zel/z80_instructions.h
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*/
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typedef struct
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{
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InstructionType type; //!< Type of the instruction.
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int16_t operand1; //!< Type of the first operand, if any.
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int16_t operand2; //!< Type of the second operand, if any.
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int16_t extra; //!< Type of third operand or tstates when a branch is taken, if applicable.
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uint8_t tstates; //!< Base number of clock ticks the instruction takes.
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uint8_t operand_types; //!< Operand layout in memory for the instruction.
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const char *format; //!< Format specifier string for disassembly.
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} InstructionTemplate;
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/*! Completely describes an instruction.
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* \headerfile z80_instructions.h zel/z80_instructions.h
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*/
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typedef struct
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{
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const InstructionTemplate *IT; //!< Template for the instruction.
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unsigned int immediate; //!< Immediate value, if any.
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unsigned int additional_tstates;//!< Additional clock ticks.
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unsigned int r_increment; //!< Amount by which the \c r register is incremented.
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int offset; //!< Offset, if any.
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} Instruction;
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/*! Instruction table for unprefixed instructions. */
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extern const InstructionTemplate Unprefixed[256];
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/*! Instruction table for cb prefixed instructions. */
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extern const InstructionTemplate CB_Prefixed[256];
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/*! Instruction table for dd prefixed instructions. */
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extern const InstructionTemplate DD_Prefixed[256];
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/*! Instruction table for ddcb prefixed instructions. */
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extern const InstructionTemplate DDCB_Prefixed[256];
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/*! Instruction table for ed prefixed instructions. */
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extern const InstructionTemplate ED_Prefixed[256];
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/*! Instruction table for fd prefixed instructions. */
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extern const InstructionTemplate FD_Prefixed[256];
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/*! Instruction table for fdcb prefixed instructions. */
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extern const InstructionTemplate FDCB_Prefixed[256];
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/*! Memory reading callback.
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* \param addr The address to read.
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* \param data Callback data from IF_ID().
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* \return The value at address \a addr.
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*/
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typedef uint8_t (*ReadMemFunction)(uint16_t addr, void *data);
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/*! Instruction fetch and instruction decode. Fetchs and decodes the
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* instruction pointed to by \a address into \a *inst.
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* \param inst Pointer to an \c Instruction. \a *inst is set to the
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* decoded instruction.
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* \param address The address of the instruction.
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* \param ReadMem Called repeatedly to get bytes of the instruction.
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* \a data is passed as the \c data argument.
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* \param data Arbitrary data passed to the \a ReadMem callback.
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* \return The length of the instruction.
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*/
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int IF_ID( Instruction *inst, uint16_t address, ReadMemFunction ReadMem, void *data );
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/*! Disassemble the instruction pointed to by \a inst into \a buffer.
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* \param inst Pointer to an \c Instruction.
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* \param buffer Buffer into which the disassembly is written. It must
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* be large enough to hold 25 bytes.
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*/
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void DisassembleInstruction( const Instruction *inst, char *buffer );
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#ifdef __cplusplus
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}
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#endif
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#endif
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