603 lines
21 KiB
Rust
603 lines
21 KiB
Rust
mod opcode;
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mod opcode_table;
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use std::{
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fmt::Display,
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ops::{Index, IndexMut},
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};
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use bitflags::bitflags;
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use opcode_table::OPCODE_TABLE;
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use self::opcode::{Opcode, Register, RegisterPair};
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bitflags! {
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub struct Status: u8 {
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const INTA = 0x1;
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const WO = 0x2;
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const STACK = 0x4;
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const HLTA = 0x8;
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const OUT = 0x10;
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const M1 = 0x20;
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const INP = 0x40;
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const MEMR = 0x80;
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}
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}
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum MemCycle {
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Fetch(u16),
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Read(u16),
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Write(u16, u8),
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StackRead(u16),
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StackWrite(u16, u8),
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In(u16),
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Out(u16, u8),
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#[allow(unused)]
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Inta(u16),
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Hlta(u16),
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#[allow(unused)]
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IntaHlt(u16),
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}
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impl MemCycle {
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pub fn get_status(self) -> Status {
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match self {
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Self::Fetch(_) => Status::WO | Status::M1 | Status::MEMR,
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Self::Read(_) => Status::WO | Status::MEMR,
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Self::Write(_, _) => Status::empty(),
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Self::StackRead(_) => Status::WO | Status::MEMR | Status::STACK,
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Self::StackWrite(_, _) => Status::STACK,
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Self::In(_) => Status::WO | Status::INP,
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Self::Out(_, _) => Status::OUT,
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Self::Inta(_) => Status::INTA | Status::WO | Status::M1,
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Self::Hlta(_) => Status::HLTA | Status::WO | Status::M1,
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Self::IntaHlt(_) => Status::INTA | Status::HLTA | Status::WO | Status::M1,
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}
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}
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pub fn address(self) -> u16 {
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match self {
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Self::Fetch(a) => a,
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Self::Read(a) => a,
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Self::Write(a, _) => a,
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Self::StackRead(a) => a,
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Self::StackWrite(a, _) => a,
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Self::In(a) => a,
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Self::Out(a, _) => a,
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Self::Inta(a) => a,
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Self::Hlta(a) => a,
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Self::IntaHlt(a) => a,
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}
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}
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}
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum MCycle {
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M1,
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M2,
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M3,
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M4,
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M5,
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}
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impl MCycle {
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fn next(self) -> Self {
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match self {
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Self::M1 => Self::M2,
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Self::M2 => Self::M3,
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Self::M3 => Self::M4,
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Self::M4 => Self::M5,
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Self::M5 => panic!(),
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}
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}
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}
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impl Display for MCycle {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match self {
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Self::M1 => f.write_str("M1"),
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Self::M2 => f.write_str("M2"),
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Self::M3 => f.write_str("M3"),
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Self::M4 => f.write_str("M4"),
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Self::M5 => f.write_str("M5"),
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}
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}
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}
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#[derive(Clone, Debug)]
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struct RegisterFile {
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b: u8,
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c: u8,
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d: u8,
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e: u8,
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h: u8,
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l: u8,
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a: u8,
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}
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impl RegisterFile {
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fn new() -> Self {
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Self {
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b: rand::random(),
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c: rand::random(),
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d: rand::random(),
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e: rand::random(),
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h: rand::random(),
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l: rand::random(),
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a: rand::random(),
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}
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}
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}
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impl Index<Register> for RegisterFile {
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type Output = u8;
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fn index(&self, index: Register) -> &Self::Output {
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match index {
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Register::B => &self.b,
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Register::C => &self.c,
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Register::D => &self.d,
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Register::E => &self.e,
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Register::H => &self.h,
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Register::L => &self.l,
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Register::A => &self.a,
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}
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}
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}
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impl IndexMut<Register> for RegisterFile {
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fn index_mut(&mut self, index: Register) -> &mut Self::Output {
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match index {
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Register::B => &mut self.b,
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Register::C => &mut self.c,
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Register::D => &mut self.d,
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Register::E => &mut self.e,
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Register::H => &mut self.h,
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Register::L => &mut self.l,
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Register::A => &mut self.a,
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}
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}
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}
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impl Default for RegisterFile {
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fn default() -> Self {
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Self::new()
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}
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}
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#[derive(Clone, Debug)]
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pub struct I8080 {
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pc: u16,
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regs: RegisterFile,
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sp: u16,
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#[allow(unused)]
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sign: bool,
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#[allow(unused)]
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zero: bool,
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#[allow(unused)]
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parity: bool,
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#[allow(unused)]
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carry: bool,
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#[allow(unused)]
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aux_carry: bool,
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cycle: MCycle,
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opcode: Opcode,
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w: u8,
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z: u8,
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tmp: u8,
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halted: bool,
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}
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impl Display for I8080 {
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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f.write_fmt(format_args!(
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"PC: {:#x} A: {:#x}, B: {:#x}, C: {:#x}, D: {:#x}, E: {:#x}, H: {:#x}, L: {:#x}, SP: {:#x}",
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self.pc,
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self.regs.a,
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self.regs.b,
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self.regs.c,
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self.regs.d,
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self.regs.e,
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self.regs.h,
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self.regs.l,
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self.sp
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))
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}
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}
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impl I8080 {
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pub fn new() -> Self {
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Self {
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pc: rand::random(),
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regs: RegisterFile::new(),
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sp: rand::random(),
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sign: rand::random(),
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zero: rand::random(),
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parity: rand::random(),
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carry: rand::random(),
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aux_carry: rand::random(),
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cycle: MCycle::M1,
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opcode: Opcode::Nop,
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w: rand::random(),
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z: rand::random(),
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tmp: rand::random(),
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halted: rand::random(),
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}
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}
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pub fn reset(&mut self) {
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self.pc = 0;
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self.halted = false;
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}
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pub fn get_mem_cycle(&self) -> MemCycle {
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if self.halted {
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return MemCycle::Hlta(self.pc);
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};
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match self.cycle {
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MCycle::M1 => MemCycle::Fetch(self.pc),
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MCycle::M2 => match self.opcode {
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Opcode::MovMR(src) => {
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MemCycle::Write(self.get_pair(RegisterPair::HL), self.regs[src])
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}
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Opcode::MovRM(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Mvi(_) => MemCycle::Read(self.pc),
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Opcode::Lxi(_) => MemCycle::Read(self.pc),
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Opcode::Lda => MemCycle::Read(self.pc),
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Opcode::Sta => MemCycle::Read(self.pc),
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Opcode::Lhld => MemCycle::Read(self.pc),
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Opcode::Shld => MemCycle::Read(self.pc),
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Opcode::Ldax(rp) => MemCycle::Read(self.get_pair(rp)),
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Opcode::Stax(rp) => MemCycle::Read(self.get_pair(rp)),
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Opcode::Add(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Adi => MemCycle::Read(self.pc),
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Opcode::Adc(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Aci => MemCycle::Read(self.pc),
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Opcode::Sub(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Sui => MemCycle::Read(self.pc),
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Opcode::Sbb(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Sbi => MemCycle::Read(self.pc),
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Opcode::Inr(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Dcr(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Ana(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Ani => MemCycle::Read(self.pc),
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Opcode::Xra(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Xri => MemCycle::Read(self.pc),
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Opcode::Ora(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Ori => MemCycle::Read(self.pc),
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Opcode::Cmp(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
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Opcode::Cpi => MemCycle::Read(self.pc),
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Opcode::Jmp => MemCycle::Read(self.pc),
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Opcode::Jcc(_) => MemCycle::Read(self.pc),
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Opcode::Call => MemCycle::Read(self.pc),
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Opcode::Ccc(_) => MemCycle::Read(self.pc),
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Opcode::Ret => MemCycle::Read(self.sp),
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Opcode::Rcc(_) => MemCycle::StackRead(self.sp),
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Opcode::Rst(_) => MemCycle::StackWrite(self.sp, (self.pc >> 8) as u8),
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Opcode::Push(_) => MemCycle::StackRead(self.sp),
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Opcode::Pop(_) => MemCycle::StackRead(self.sp),
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Opcode::Xthl => MemCycle::StackRead(self.sp),
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Opcode::In => MemCycle::Read(self.pc),
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Opcode::Out => MemCycle::Read(self.pc),
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_ => unreachable!(),
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},
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MCycle::M3 => match self.opcode {
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Opcode::Mvi(_) => MemCycle::Write(self.get_pair(RegisterPair::HL), self.tmp),
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Opcode::Lxi(_) => MemCycle::Read(self.pc),
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Opcode::Lda => MemCycle::Read(self.pc),
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Opcode::Sta => MemCycle::Read(self.pc),
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Opcode::Lhld => MemCycle::Read(self.pc),
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Opcode::Shld => MemCycle::Read(self.pc),
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Opcode::Inr(_) => MemCycle::Write(self.get_pair(RegisterPair::HL), self.tmp),
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Opcode::Dcr(_) => MemCycle::Write(self.get_pair(RegisterPair::HL), self.tmp),
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Opcode::Jmp => MemCycle::Read(self.pc),
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Opcode::Jcc(_) => MemCycle::Read(self.pc),
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Opcode::Call => MemCycle::Read(self.pc),
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Opcode::Ccc(_) => MemCycle::Read(self.pc),
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Opcode::Ret => MemCycle::StackRead(self.sp),
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Opcode::Rcc(_) => MemCycle::StackRead(self.sp),
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Opcode::Rst(_) => MemCycle::StackWrite(self.sp, 0),
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Opcode::Xthl => MemCycle::StackRead(self.sp),
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Opcode::In => MemCycle::In(self.get_wz()),
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Opcode::Out => MemCycle::Out(self.get_wz(), self.regs.a),
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_ => unreachable!(),
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},
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MCycle::M4 => match self.opcode {
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Opcode::Lda => MemCycle::Read(self.get_wz()),
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Opcode::Sta => MemCycle::Write(self.get_wz(), self.regs.a),
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Opcode::Lhld => MemCycle::Read(self.get_wz()),
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Opcode::Shld => MemCycle::Write(self.get_wz(), self.regs.l),
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Opcode::Call => MemCycle::StackWrite(self.sp, (self.pc >> 8) as u8),
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Opcode::Ccc(_) => MemCycle::StackWrite(self.sp, (self.pc >> 8) as u8),
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Opcode::Xthl => MemCycle::StackWrite(self.sp, self.regs.h),
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_ => unreachable!(),
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},
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MCycle::M5 => match self.opcode {
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Opcode::Lhld => MemCycle::Read(self.get_wz()),
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Opcode::Shld => MemCycle::Write(self.get_wz(), self.regs.h),
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Opcode::Call => MemCycle::StackWrite(self.sp, self.pc as u8),
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Opcode::Ccc(_) => MemCycle::StackWrite(self.sp, self.pc as u8),
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Opcode::Xthl => MemCycle::StackWrite(self.sp, self.regs.l),
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_ => unreachable!(),
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},
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}
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}
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pub fn finish_m_cycle(&mut self, data: u8) {
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if self.halted {
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return;
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}
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println!(
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"Finish {} ({:?}), got data {}",
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self.cycle,
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self.get_mem_cycle(),
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data
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);
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match self.cycle {
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MCycle::M1 => {
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self.pc += 1;
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self.opcode = OPCODE_TABLE[data as usize];
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dbg!(self.opcode);
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match self.opcode {
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Opcode::MovMR(_) => (),
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Opcode::MovRM(_) => (),
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Opcode::Mov(dst, src) => {
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self.regs[dst] = self.regs[src];
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}
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Opcode::Sphl => {
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self.sp = ((self.regs.h as u16) << 8) | (self.regs.l as u16);
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}
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Opcode::MviM => (),
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Opcode::Mvi(_) => (),
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Opcode::Lxi(_) => (),
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Opcode::Lda => (),
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Opcode::Sta => (),
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Opcode::Lhld => (),
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Opcode::Shld => (),
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Opcode::Ldax(_) => (),
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Opcode::Stax(_) => (),
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Opcode::Xchg => {
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(self.regs.d, self.regs.e, self.regs.h, self.regs.l) =
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(self.regs.h, self.regs.l, self.regs.d, self.regs.e);
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}
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Opcode::AddM => (),
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Opcode::Add(src) => {
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let a = self.regs.a;
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let b = self.regs[src];
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let res = (a as u16) + (b as u16);
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self.sign = ((res as u8) & 0x80) > 0;
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self.zero = (res as u8) == 0;
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self.aux_carry = (a & 0x0f) + (b & 0x0f) > 0x0f;
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self.parity = (res as u8).count_ones() % 2 == 0;
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self.carry = res > 0xff;
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self.regs.a = res as u8;
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}
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Opcode::Adi => (),
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Opcode::AdcM => (),
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Opcode::Adc(_) => todo!(),
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Opcode::Aci => (),
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Opcode::SubM => (),
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Opcode::Sub(_) => todo!(),
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Opcode::Sui => (),
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Opcode::SbbM => (),
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Opcode::Sbb(_) => todo!(),
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Opcode::Sbi => (),
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Opcode::InrM => (),
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Opcode::Inr(_) => todo!(),
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Opcode::DcrM => (),
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Opcode::Dcr(_) => todo!(),
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Opcode::Inx(dst) => self.set_pair(dst, self.get_pair(dst) + 1),
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Opcode::Dcx(dst) => self.set_pair(dst, self.get_pair(dst) + 2),
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Opcode::Dad(src) => {
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let a = self.get_pair(RegisterPair::HL) as u32;
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let b = self.get_pair(src) as u32;
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let res = a + b;
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self.carry = res > 0xffff;
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self.set_pair(RegisterPair::HL, res as u16);
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}
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Opcode::Daa => todo!(),
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Opcode::AnaM => (),
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Opcode::Ana(_) => todo!(),
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Opcode::Ani => (),
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Opcode::XraM => (),
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Opcode::Xra(_) => todo!(),
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Opcode::Xri => (),
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Opcode::OraM => (),
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Opcode::Ora(_) => todo!(),
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Opcode::Ori => (),
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Opcode::CmpM => (),
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Opcode::Cmp(_) => todo!(),
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Opcode::Cpi => (),
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Opcode::Rlc => todo!(),
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Opcode::Rrc => todo!(),
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Opcode::Ral => todo!(),
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Opcode::Rar => todo!(),
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Opcode::Cma => todo!(),
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Opcode::Cmc => todo!(),
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Opcode::Stc => todo!(),
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Opcode::Jmp => (),
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Opcode::Jcc(_) => todo!(),
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Opcode::Call => todo!(),
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Opcode::Ccc(_) => todo!(),
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Opcode::Ret => (),
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Opcode::Rcc(_) => todo!(),
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Opcode::Rst(_) => todo!(),
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Opcode::Pchl => todo!(),
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Opcode::Push(_) => todo!(),
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Opcode::Pop(_) => (),
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Opcode::Xthl => (),
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Opcode::In => (),
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Opcode::Out => (),
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Opcode::Ei => todo!(),
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Opcode::Di => todo!(),
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Opcode::Hlt => self.halted = true,
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Opcode::Nop => (),
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}
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}
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MCycle::M2 => match self.opcode {
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Opcode::MovMR(_) => (),
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Opcode::MovRM(dst) => self.regs[dst] = data,
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Opcode::MviM => {
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self.pc += 1;
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self.tmp = data;
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}
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Opcode::Mvi(dst) => {
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self.regs[dst] = data;
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}
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Opcode::Lxi(_) => todo!(),
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Opcode::Lda => {
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self.z = data;
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self.pc += 1;
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}
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Opcode::Sta => {
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self.z = data;
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self.pc += 1;
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}
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Opcode::Lhld => todo!(),
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Opcode::Shld => todo!(),
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Opcode::Ldax(_) => todo!(),
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Opcode::Stax(_) => todo!(),
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Opcode::AddM => {
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let a = self.regs.a;
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let b = data;
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let res = (a as u16) + (b as u16);
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self.sign = ((res as u8) & 0x80) > 0;
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self.zero = (res as u8) == 0;
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self.aux_carry = (a & 0x0f) + (b & 0x0f) > 0x0f;
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self.parity = (res as u8).count_ones() % 2 == 0;
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self.carry = res > 0xff;
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self.regs.a = res as u8;
|
|
}
|
|
Opcode::Adi => todo!(),
|
|
Opcode::AdcM => todo!(),
|
|
Opcode::Aci => todo!(),
|
|
Opcode::SubM => todo!(),
|
|
Opcode::Sui => todo!(),
|
|
Opcode::SbbM => todo!(),
|
|
Opcode::Sbi => todo!(),
|
|
Opcode::InrM => todo!(),
|
|
Opcode::DcrM => todo!(),
|
|
Opcode::AnaM => todo!(),
|
|
Opcode::Ani => todo!(),
|
|
Opcode::XraM => todo!(),
|
|
Opcode::Xri => todo!(),
|
|
Opcode::OraM => todo!(),
|
|
Opcode::Ori => todo!(),
|
|
Opcode::CmpM => todo!(),
|
|
Opcode::Cpi => todo!(),
|
|
Opcode::Jmp => {
|
|
self.z = data;
|
|
self.pc += 1;
|
|
}
|
|
Opcode::Jcc(_) => todo!(),
|
|
Opcode::Call => todo!(),
|
|
Opcode::Ccc(_) => todo!(),
|
|
Opcode::Ret => todo!(),
|
|
Opcode::Rcc(_) => todo!(),
|
|
Opcode::Rst(_) => todo!(),
|
|
Opcode::Push(_) => todo!(),
|
|
Opcode::Pop(_) => todo!(),
|
|
Opcode::Xthl => {
|
|
self.sp += 1;
|
|
self.z = data;
|
|
}
|
|
Opcode::In => todo!(),
|
|
Opcode::Out => todo!(),
|
|
Opcode::Hlt => todo!(),
|
|
_ => unreachable!(),
|
|
},
|
|
MCycle::M3 => match self.opcode {
|
|
Opcode::MviM => (),
|
|
Opcode::Lxi(_) => todo!(),
|
|
Opcode::Lda => {
|
|
self.w = data;
|
|
self.pc += 1;
|
|
}
|
|
Opcode::Sta => {
|
|
self.w = data;
|
|
self.pc += 1;
|
|
}
|
|
Opcode::Lhld => todo!(),
|
|
Opcode::Shld => {
|
|
self.set_wz(self.get_wz() + 1);
|
|
}
|
|
Opcode::Inr(_) => todo!(),
|
|
Opcode::Dcr(_) => todo!(),
|
|
Opcode::Jmp => {
|
|
self.w = data;
|
|
self.pc = self.get_wz();
|
|
}
|
|
Opcode::Jcc(_) => todo!(),
|
|
Opcode::Call => todo!(),
|
|
Opcode::Ccc(_) => todo!(),
|
|
Opcode::Ret => todo!(),
|
|
Opcode::Rcc(_) => todo!(),
|
|
Opcode::Rst(_) => todo!(),
|
|
_ => unreachable!(),
|
|
},
|
|
MCycle::M4 => match self.opcode {
|
|
Opcode::Lda => {
|
|
self.regs.a = data;
|
|
}
|
|
Opcode::Sta => (),
|
|
Opcode::Lhld => todo!(),
|
|
Opcode::Shld => todo!(),
|
|
Opcode::Call => todo!(),
|
|
Opcode::Ccc(_) => todo!(),
|
|
Opcode::Xthl => (),
|
|
_ => unreachable!(),
|
|
},
|
|
MCycle::M5 => match self.opcode {
|
|
Opcode::Call => todo!(),
|
|
Opcode::Ccc(_) => todo!(),
|
|
Opcode::Xthl => (),
|
|
_ => unreachable!(),
|
|
},
|
|
}
|
|
if self.cycle == self.opcode.max_m_cycle() {
|
|
println!("Instruction done");
|
|
self.cycle = MCycle::M1;
|
|
} else {
|
|
self.cycle = self.cycle.next();
|
|
}
|
|
}
|
|
|
|
fn get_pair(&self, pair: RegisterPair) -> u16 {
|
|
match pair {
|
|
RegisterPair::BC => ((self.regs.b as u16) << 8) | (self.regs.c as u16),
|
|
RegisterPair::DE => ((self.regs.d as u16) << 8) | (self.regs.e as u16),
|
|
RegisterPair::HL => ((self.regs.h as u16) << 8) | (self.regs.l as u16),
|
|
RegisterPair::SP => self.sp,
|
|
}
|
|
}
|
|
|
|
fn get_wz(&self) -> u16 {
|
|
((self.w as u16) << 8) | (self.z as u16)
|
|
}
|
|
|
|
fn set_pair(&mut self, pair: RegisterPair, val: u16) {
|
|
match pair {
|
|
RegisterPair::BC => {
|
|
self.regs.b = (val >> 8) as u8;
|
|
self.regs.c = val as u8;
|
|
}
|
|
RegisterPair::DE => {
|
|
self.regs.d = (val >> 8) as u8;
|
|
self.regs.e = val as u8;
|
|
}
|
|
RegisterPair::HL => {
|
|
self.regs.h = (val >> 8) as u8;
|
|
self.regs.l = val as u8;
|
|
}
|
|
RegisterPair::SP => self.sp = val,
|
|
}
|
|
}
|
|
|
|
fn set_wz(&mut self, val: u16) {
|
|
self.w = (val >> 8) as u8;
|
|
self.z = val as u8;
|
|
}
|
|
}
|