Fix reset not resetting M-cycle

2024-02-01 19:15:09 -06:00 · 2024-02-01 19:15:09 -06:00 · 63de2cf5ae
commit 63de2cf5ae
parent 0b3e2d0ff3
1 changed files with 1 additions and 0 deletions
--- a/src/cpu.rs
+++ b/src/cpu.rs
@ -234,6 +234,7 @@ impl I8080 {
        self.pc = 0;
        self.halted = false;
        self.inte = false;
+        self.cycle = MCycle::M1;
    }

    pub fn get_mem_cycle(&self) -> MemCycle {