pjht/altair_emu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Implement all opcodes

Browse Source
This commit is contained in:
pjht 2024-01-23 16:01:14 -06:00
parent ac347f3613
commit 0c937d6b89
Signed by: pjht
GPG Key ID: CA239FC6934E6F3A
2 changed files with 62 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

74
src/cpu.rs
View File

@ -247,6 +247,7 @@ impl I8080 {
MemCycle::Write(self.get_pair(RegisterPair::HL), self.regs[src]) MemCycle::Write(self.get_pair(RegisterPair::HL), self.regs[src])
} }
Opcode::MovRM(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::MovRM(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::MviM => MemCycle::Read(self.pc),
Opcode::Mvi(_) => MemCycle::Read(self.pc), Opcode::Mvi(_) => MemCycle::Read(self.pc),
Opcode::Lxi(_) => MemCycle::Read(self.pc), Opcode::Lxi(_) => MemCycle::Read(self.pc),
Opcode::Lda => MemCycle::Read(self.pc), Opcode::Lda => MemCycle::Read(self.pc),
@ -255,23 +256,23 @@ impl I8080 {
Opcode::Shld => MemCycle::Read(self.pc), Opcode::Shld => MemCycle::Read(self.pc),
Opcode::Ldax(rp) => MemCycle::Read(self.get_pair(rp)), Opcode::Ldax(rp) => MemCycle::Read(self.get_pair(rp)),
Opcode::Stax(rp) => MemCycle::Write(self.get_pair(rp), self.regs.a), Opcode::Stax(rp) => MemCycle::Write(self.get_pair(rp), self.regs.a),
Opcode::Add(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::AddM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Adi => MemCycle::Read(self.pc), Opcode::Adi => MemCycle::Read(self.pc),
Opcode::Adc(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::AdcM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Aci => MemCycle::Read(self.pc), Opcode::Aci => MemCycle::Read(self.pc),
Opcode::Sub(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::SubM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Sui => MemCycle::Read(self.pc), Opcode::Sui => MemCycle::Read(self.pc),
Opcode::Sbb(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::SbbM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Sbi => MemCycle::Read(self.pc), Opcode::Sbi => MemCycle::Read(self.pc),
Opcode::InrM => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::InrM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::DcrM => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::DcrM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Ana(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::AnaM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Ani => MemCycle::Read(self.pc), Opcode::Ani => MemCycle::Read(self.pc),
Opcode::Xra(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::XraM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Xri => MemCycle::Read(self.pc), Opcode::Xri => MemCycle::Read(self.pc),
Opcode::Ora(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::OraM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Ori => MemCycle::Read(self.pc), Opcode::Ori => MemCycle::Read(self.pc),
Opcode::Cmp(_) => MemCycle::Read(self.get_pair(RegisterPair::HL)), Opcode::CmpM => MemCycle::Read(self.get_pair(RegisterPair::HL)),
Opcode::Cpi => MemCycle::Read(self.pc), Opcode::Cpi => MemCycle::Read(self.pc),
Opcode::Jmp => MemCycle::Read(self.pc), Opcode::Jmp => MemCycle::Read(self.pc),
Opcode::Call => MemCycle::Read(self.pc), Opcode::Call => MemCycle::Read(self.pc),
@ -287,7 +288,7 @@ impl I8080 {
_ => unreachable!(), _ => unreachable!(),
}, },
MCycle::M3 => match self.opcode { MCycle::M3 => match self.opcode {
Opcode::Mvi(_) => MemCycle::Write(self.get_pair(RegisterPair::HL), self.tmp), Opcode::MviM => MemCycle::Write(self.get_pair(RegisterPair::HL), self.tmp),
Opcode::Lxi(_) => MemCycle::Read(self.pc), Opcode::Lxi(_) => MemCycle::Read(self.pc),
Opcode::Lda => MemCycle::Read(self.pc), Opcode::Lda => MemCycle::Read(self.pc),
Opcode::Sta => MemCycle::Read(self.pc), Opcode::Sta => MemCycle::Read(self.pc),
@ -415,7 +416,18 @@ impl I8080 {
self.carry = res > 0xffff; self.carry = res > 0xffff;
self.set_pair(RegisterPair::HL, res as u16); self.set_pair(RegisterPair::HL, res as u16);
} }
Opcode::Daa => todo!(), Opcode::Daa => {
if self.aux_carry || (self.regs.a & 0xF > 0x9) {
let (ac, cy, res) = Self::add_8bit(self.regs.a, 0x6);
self.update_arith_flags(ac, cy, res);
self.regs.a = res;
}
if self.carry || (self.regs.a & 0xF0 > 0x90) {
let (ac, cy, res) = Self::add_8bit(self.regs.a, 0x6);
self.update_arith_flags(ac, cy, res);
self.regs.a = res;
}
},
Opcode::AnaM => (), Opcode::AnaM => (),
Opcode::Ana(src) => { Opcode::Ana(src) => {
self.regs.a &= self.regs[src]; self.regs.a &= self.regs[src];
@ -440,13 +452,35 @@ impl I8080 {
self.update_arith_flags(ac, cy, res); self.update_arith_flags(ac, cy, res);
} }
Opcode::Cpi => (), Opcode::Cpi => (),
Opcode::Rlc => todo!(), Opcode::Rlc => {
Opcode::Rrc => todo!(), self.regs.a = self.regs.a.rotate_left(1);
Opcode::Ral => todo!(), self.carry = (self.regs.a & 0x1) > 0;
Opcode::Rar => todo!(), },
Opcode::Cma => todo!(), Opcode::Rrc => {
Opcode::Cmc => todo!(), self.regs.a = self.regs.a.rotate_right(1);
Opcode::Stc => todo!(), self.carry = (self.regs.a & 0x80) > 0;
},
Opcode::Ral => {
let high_bit = (self.regs.a & 0x80) > 0;
self.regs.a = self.regs.a << 1;
self.regs.a |= self.carry as u8;
self.carry = high_bit;
},
Opcode::Rar => {
let low_bit = (self.regs.a & 0x1) > 0;
self.regs.a = self.regs.a >> 1;
self.regs.a |= (self.carry as u8) << 7;
self.carry = low_bit;
},
Opcode::Cma => {
self.regs.a = !self.regs.a;
},
Opcode::Cmc => {
self.carry = !self.carry;
},
Opcode::Stc => {
self.carry = true;
},
Opcode::Jmp => (), Opcode::Jmp => (),
Opcode::Jcc(cc) => { Opcode::Jcc(cc) => {
cond_failed = !self.check_cond(cc); cond_failed = !self.check_cond(cc);
@ -496,7 +530,9 @@ impl I8080 {
Opcode::Di => { Opcode::Di => {
self.inte = false; self.inte = false;
} }
Opcode::Hlt => self.halted = true, Opcode::Hlt => {
self.halted = true;
},
Opcode::Nop => (), Opcode::Nop => (),
} }
} }
@ -723,6 +759,8 @@ impl I8080 {
Opcode::Xthl => { Opcode::Xthl => {
self.w = data; self.w = data;
} }
Opcode::In => (),
Opcode::Out => (),
_ => unreachable!(), _ => unreachable!(),
}, },
MCycle::M4 => match self.opcode { MCycle::M4 => match self.opcode {

9
src/main.rs
View File

@ -284,7 +284,10 @@ impl AltairEmulator {
self.fp_address = a; self.fp_address = a;
self.fp_data = 0xff; self.fp_data = 0xff;
} }
MemCycle::In(_) => todo!(), MemCycle::In(a) => {
self.fp_address = a;
self.fp_data = 0;
},
MemCycle::Inta(_) => todo!(), MemCycle::Inta(_) => todo!(),
MemCycle::Hlta(_) => { MemCycle::Hlta(_) => {
self.fp_data = 0xff; self.fp_data = 0xff;
@ -671,8 +674,8 @@ impl eframe::App for AltairEmulator {
self.mem[a as usize] = d; self.mem[a as usize] = d;
0 0
} }
MemCycle::In(_) => todo!(), MemCycle::In(_) => 0,
MemCycle::Out(_, _) => todo!(), MemCycle::Out(_, _) => 0,
MemCycle::Inta(_) => todo!(), MemCycle::Inta(_) => todo!(),
MemCycle::Hlta(_) => { MemCycle::Hlta(_) => {
self.running = false; self.running = false;