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Add riscv arch def

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This commit is contained in:
Gary Guo 2021-08-26 12:38:45 +01:00
parent 62878b5995
commit 2212467faf
2 changed files with 35 additions and 17 deletions
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35
src/arch.rs Normal file
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@ -0,0 +1,35 @@
#[cfg(target_arch = "x86_64")]
mod x86_64 {
use gimli::{Register, X86_64};
pub struct Arch;
#[allow(unused)]
impl Arch {
pub const SP: Register = X86_64::RSP;
pub const RA: Register = X86_64::RA;
pub const UNWIND_DATA_REG: (Register, Register) = (X86_64::RAX, X86_64::RDX);
pub const UNWIND_PRIVATE_DATA_SIZE: usize = 6;
}
}
#[cfg(target_arch = "x86_64")]
pub use x86_64::*;
#[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))]
mod riscv {
use gimli::{Register, RiscV};
pub struct Arch;
#[allow(unused)]
impl Arch {
pub const SP: Register = RiscV::SP;
pub const RA: Register = RiscV::RA;
pub const UNWIND_DATA_REG: (Register, Register) = (RiscV::A0, RiscV::A1);
pub const UNWIND_PRIVATE_DATA_SIZE: usize = 2;
}
}
#[cfg(any(target_arch = "riscv64", target_arch = "riscv32"))]
pub use riscv::*;

17
src/arch/mod.rs
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@ -1,17 +0,0 @@
#[cfg(target_arch = "x86_64")]
mod x86_64 {
use gimli::{Register, X86_64};
pub struct Arch;
#[allow(unused)]
impl Arch {
pub const SP: Register = X86_64::RSP;
pub const RA: Register = X86_64::RA;
pub const UNWIND_DATA_REG: (Register, Register) = (X86_64::RAX, X86_64::RDX);
pub const UNWIND_PRIVATE_DATA_SIZE: usize = 6;
}
}
#[cfg(target_arch = "x86_64")]
pub use x86_64::*;