349 lines
11 KiB
Rust
349 lines
11 KiB
Rust
//! This module implements minimal run-time feature detection for x86.
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//!
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//! The features are detected using the `detect_features` function below.
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//! This function uses the CPUID instruction to read the feature flags from the
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//! CPU and encodes them in an `usize` where each bit position represents
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//! whether a feature is available (bit is set) or unavaiable (bit is cleared).
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//!
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//! The enum `Feature` is used to map bit positions to feature names, and the
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//! the `__crate::detect::check_for!` macro is used to map string literals (e.g.,
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//! "avx") to these bit positions (e.g., `Feature::avx`).
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//!
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//! The run-time feature detection is performed by the
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//! `__crate::detect::check_for(Feature) -> bool` function. On its first call,
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//! this functions queries the CPU for the available features and stores them
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//! in a global `AtomicUsize` variable. The query is performed by just checking
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//! whether the feature bit in this global variable is set or cleared.
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/// A macro to test at *runtime* whether a CPU feature is available on
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/// x86/x86-64 platforms.
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///
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/// This macro is provided in the standard library and will detect at runtime
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/// whether the specified CPU feature is detected. This does **not** resolve at
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/// compile time unless the specified feature is already enabled for the entire
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/// crate. Runtime detection currently relies mostly on the `cpuid` instruction.
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///
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/// This macro only takes one argument which is a string literal of the feature
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/// being tested for. The feature names supported are the lowercase versions of
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/// the ones defined by Intel in [their documentation][docs].
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///
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/// ## Supported arguments
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///
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/// This macro supports the same names that `#[target_feature]` supports. Unlike
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/// `#[target_feature]`, however, this macro does not support names separated
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/// with a comma. Instead testing for multiple features must be done through
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/// separate macro invocations for now.
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///
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/// Supported arguments are:
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///
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/// * `"aes"`
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/// * `"pclmulqdq"`
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/// * `"rdrand"`
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/// * `"rdseed"`
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/// * `"tsc"`
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/// * `"mmx"`
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/// * `"sse"`
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/// * `"sse2"`
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/// * `"sse3"`
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/// * `"ssse3"`
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/// * `"sse4.1"`
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/// * `"sse4.2"`
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/// * `"sse4a"`
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/// * `"sha"`
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/// * `"avx"`
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/// * `"avx2"`
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/// * `"avx512f"`
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/// * `"avx512cd"`
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/// * `"avx512er"`
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/// * `"avx512pf"`
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/// * `"avx512bw"`
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/// * `"avx512dq"`
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/// * `"avx512vl"`
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/// * `"avx512ifma"`
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/// * `"avx512vbmi"`
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/// * `"avx512vpopcntdq"`
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/// * `"f16c"`
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/// * `"fma"`
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/// * `"bmi1"`
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/// * `"bmi2"`
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/// * `"abm"`
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/// * `"lzcnt"`
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/// * `"tbm"`
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/// * `"popcnt"`
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/// * `"fxsr"`
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/// * `"xsave"`
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/// * `"xsaveopt"`
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/// * `"xsaves"`
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/// * `"xsavec"`
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/// * `"adx"`
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/// * `"rtm"`
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///
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/// [docs]: https://software.intel.com/sites/landingpage/IntrinsicsGuide
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#[macro_export]
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#[stable(feature = "simd_x86", since = "1.27.0")]
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#[allow_internal_unstable(stdsimd_internal,stdsimd)]
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macro_rules! is_x86_feature_detected {
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("aes") => {
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cfg!(target_feature = "aes") || $crate::detect::check_for(
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$crate::detect::Feature::aes) };
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("pclmulqdq") => {
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cfg!(target_feature = "pclmulqdq") || $crate::detect::check_for(
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$crate::detect::Feature::pclmulqdq) };
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("rdrand") => {
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cfg!(target_feature = "rdrand") || $crate::detect::check_for(
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$crate::detect::Feature::rdrand) };
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("rdseed") => {
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cfg!(target_feature = "rdseed") || $crate::detect::check_for(
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$crate::detect::Feature::rdseed) };
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("tsc") => {
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cfg!(target_feature = "tsc") || $crate::detect::check_for(
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$crate::detect::Feature::tsc) };
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("mmx") => {
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cfg!(target_feature = "mmx") || $crate::detect::check_for(
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$crate::detect::Feature::mmx) };
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("sse") => {
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cfg!(target_feature = "sse") || $crate::detect::check_for(
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$crate::detect::Feature::sse) };
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("sse2") => {
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cfg!(target_feature = "sse2") || $crate::detect::check_for(
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$crate::detect::Feature::sse2)
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};
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("sse3") => {
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cfg!(target_feature = "sse3") || $crate::detect::check_for(
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$crate::detect::Feature::sse3)
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};
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("ssse3") => {
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cfg!(target_feature = "ssse3") || $crate::detect::check_for(
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$crate::detect::Feature::ssse3)
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};
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("sse4.1") => {
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cfg!(target_feature = "sse4.1") || $crate::detect::check_for(
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$crate::detect::Feature::sse4_1)
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};
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("sse4.2") => {
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cfg!(target_feature = "sse4.2") || $crate::detect::check_for(
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$crate::detect::Feature::sse4_2)
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};
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("sse4a") => {
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cfg!(target_feature = "sse4a") || $crate::detect::check_for(
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$crate::detect::Feature::sse4a)
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};
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("sha") => {
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cfg!(target_feature = "sha") || $crate::detect::check_for(
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$crate::detect::Feature::sha)
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};
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("avx") => {
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cfg!(target_feature = "avx") || $crate::detect::check_for(
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$crate::detect::Feature::avx)
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};
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("avx2") => {
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cfg!(target_feature = "avx2") || $crate::detect::check_for(
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$crate::detect::Feature::avx2)
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};
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("avx512f") => {
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cfg!(target_feature = "avx512f") || $crate::detect::check_for(
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$crate::detect::Feature::avx512f)
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};
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("avx512cd") => {
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cfg!(target_feature = "avx512cd") || $crate::detect::check_for(
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$crate::detect::Feature::avx512cd)
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};
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("avx512er") => {
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cfg!(target_feature = "avx512er") || $crate::detect::check_for(
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$crate::detect::Feature::avx512er)
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};
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("avx512pf") => {
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cfg!(target_feature = "avx512pf") || $crate::detect::check_for(
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$crate::detect::Feature::avx512pf)
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};
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("avx512bw") => {
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cfg!(target_feature = "avx512bw") || $crate::detect::check_for(
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$crate::detect::Feature::avx512bw)
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};
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("avx512dq") => {
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cfg!(target_feature = "avx512dq") || $crate::detect::check_for(
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$crate::detect::Feature::avx512dq)
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};
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("avx512vl") => {
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cfg!(target_Feature = "avx512vl") || $crate::detect::check_for(
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$crate::detect::Feature::avx512vl)
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};
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("avx512ifma") => {
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cfg!(target_feature = "avx512ifma") || $crate::detect::check_for(
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$crate::detect::Feature::avx512_ifma)
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};
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("avx512vbmi") => {
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cfg!(target_feature = "avx512vbmi") || $crate::detect::check_for(
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$crate::detect::Feature::avx512_vbmi)
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};
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("avx512vpopcntdq") => {
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cfg!(target_feature = "avx512vpopcntdq") || $crate::detect::check_for(
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$crate::detect::Feature::avx512_vpopcntdq)
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};
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("f16c") => {
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cfg!(target_feature = "f16c") || $crate::detect::check_for(
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$crate::detect::Feature::f16c)
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};
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("fma") => {
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cfg!(target_feature = "fma") || $crate::detect::check_for(
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$crate::detect::Feature::fma)
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};
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("bmi1") => {
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cfg!(target_feature = "bmi1") || $crate::detect::check_for(
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$crate::detect::Feature::bmi)
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};
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("bmi2") => {
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cfg!(target_feature = "bmi2") || $crate::detect::check_for(
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$crate::detect::Feature::bmi2)
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};
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("abm") => {
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cfg!(target_feature = "abm") || $crate::detect::check_for(
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$crate::detect::Feature::abm)
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};
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("lzcnt") => {
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cfg!(target_feature = "lzcnt") || $crate::detect::check_for(
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$crate::detect::Feature::abm)
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};
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("tbm") => {
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cfg!(target_feature = "tbm") || $crate::detect::check_for(
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$crate::detect::Feature::tbm)
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};
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("popcnt") => {
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cfg!(target_feature = "popcnt") || $crate::detect::check_for(
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$crate::detect::Feature::popcnt)
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};
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("fxsr") => {
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cfg!(target_feature = "fxsr") || $crate::detect::check_for(
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$crate::detect::Feature::fxsr)
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};
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("xsave") => {
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cfg!(target_feature = "xsave") || $crate::detect::check_for(
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$crate::detect::Feature::xsave)
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};
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("xsaveopt") => {
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cfg!(target_feature = "xsaveopt") || $crate::detect::check_for(
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$crate::detect::Feature::xsaveopt)
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};
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("xsaves") => {
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cfg!(target_feature = "xsaves") || $crate::detect::check_for(
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$crate::detect::Feature::xsaves)
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};
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("xsavec") => {
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cfg!(target_feature = "xsavec") || $crate::detect::check_for(
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$crate::detect::Feature::xsavec)
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};
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("cmpxchg16b") => {
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cfg!(target_feature = "cmpxchg16b") || $crate::detect::check_for(
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$crate::detect::Feature::cmpxchg16b)
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};
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("adx") => {
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cfg!(target_feature = "adx") || $crate::detect::check_for(
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$crate::detect::Feature::adx)
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};
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("rtm") => {
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cfg!(target_feature = "rtm") || $crate::detect::check_for(
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$crate::detect::Feature::rtm)
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};
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($t:tt,) => {
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is_x86_feature_detected!($t);
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};
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($t:tt) => {
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compile_error!(concat!("unknown target feature: ", $t))
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};
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}
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/// X86 CPU Feature enum. Each variant denotes a position in a bitset for a
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/// particular feature.
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///
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/// This is an unstable implementation detail subject to change.
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#[allow(non_camel_case_types)]
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#[repr(u8)]
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#[doc(hidden)]
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#[unstable(feature = "stdsimd_internal", issue = "0")]
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pub enum Feature {
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/// AES (Advanced Encryption Standard New Instructions AES-NI)
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aes,
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/// CLMUL (Carry-less Multiplication)
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pclmulqdq,
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/// RDRAND
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rdrand,
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/// RDSEED
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rdseed,
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/// TSC (Time Stamp Counter)
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tsc,
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/// MMX
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mmx,
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/// SSE (Streaming SIMD Extensions)
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sse,
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/// SSE2 (Streaming SIMD Extensions 2)
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sse2,
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/// SSE3 (Streaming SIMD Extensions 3)
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sse3,
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/// SSSE3 (Supplemental Streaming SIMD Extensions 3)
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ssse3,
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/// SSE4.1 (Streaming SIMD Extensions 4.1)
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sse4_1,
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/// SSE4.2 (Streaming SIMD Extensions 4.2)
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sse4_2,
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/// SSE4a (Streaming SIMD Extensions 4a)
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sse4a,
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/// SHA
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sha,
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/// AVX (Advanced Vector Extensions)
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avx,
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/// AVX2 (Advanced Vector Extensions 2)
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avx2,
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/// AVX-512 F (Foundation)
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avx512f,
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/// AVX-512 CD (Conflict Detection Instructions)
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avx512cd,
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/// AVX-512 ER (Exponential and Reciprocal Instructions)
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avx512er,
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/// AVX-512 PF (Prefetch Instructions)
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avx512pf,
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/// AVX-512 BW (Byte and Word Instructions)
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avx512bw,
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/// AVX-512 DQ (Doubleword and Quadword)
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avx512dq,
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/// AVX-512 VL (Vector Length Extensions)
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avx512vl,
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/// AVX-512 IFMA (Integer Fused Multiply Add)
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avx512_ifma,
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/// AVX-512 VBMI (Vector Byte Manipulation Instructions)
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avx512_vbmi,
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/// AVX-512 VPOPCNTDQ (Vector Population Count Doubleword and
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/// Quadword)
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avx512_vpopcntdq,
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/// F16C (Conversions between IEEE-754 `binary16` and `binary32` formats)
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f16c,
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/// FMA (Fused Multiply Add)
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fma,
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/// BMI1 (Bit Manipulation Instructions 1)
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bmi,
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/// BMI1 (Bit Manipulation Instructions 2)
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bmi2,
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/// ABM (Advanced Bit Manipulation) on AMD / LZCNT (Leading Zero
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/// Count) on Intel
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abm,
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/// TBM (Trailing Bit Manipulation)
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tbm,
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/// POPCNT (Population Count)
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popcnt,
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/// FXSR (Floating-point context fast save and restor)
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fxsr,
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/// XSAVE (Save Processor Extended States)
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xsave,
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/// XSAVEOPT (Save Processor Extended States Optimized)
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xsaveopt,
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/// XSAVES (Save Processor Extended States Supervisor)
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xsaves,
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/// XSAVEC (Save Processor Extended States Compacted)
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xsavec,
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/// CMPXCH16B, a 16-byte compare-and-swap instruction
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cmpxchg16b,
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/// ADX, Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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adx,
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/// RTM, Intel (Restricted Transactional Memory)
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rtm,
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}
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