158 lines
6.4 KiB
Rust
158 lines
6.4 KiB
Rust
use crate::simd::{LaneCount, Simd, SupportedLaneCount};
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use core::mem;
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impl<const N: usize> Simd<u8, N>
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where
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LaneCount<N>: SupportedLaneCount,
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{
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/// Swizzle a vector of bytes according to the index vector.
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/// Indices within range select the appropriate byte.
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/// Indices "out of bounds" instead select 0.
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///
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/// Note that the current implementation is selected during build-time
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/// of the standard library, so `cargo build -Zbuild-std` may be necessary
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/// to unlock better performance, especially for larger vectors.
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/// A planned compiler improvement will enable using `#[target_feature]` instead.
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#[inline]
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pub fn swizzle_dyn(self, idxs: Simd<u8, N>) -> Self {
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#![allow(unused_imports, unused_unsafe)]
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#[cfg(target_arch = "aarch64")]
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use core::arch::aarch64::{uint8x8_t, vqtbl1q_u8, vtbl1_u8};
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#[cfg(all(target_arch = "arm", target_feature = "v7", target_feature = "neon"))]
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use core::arch::arm::{uint8x8_t, vtbl1_u8};
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#[cfg(target_arch = "wasm32")]
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use core::arch::wasm32 as wasm;
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#[cfg(target_arch = "x86")]
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use core::arch::x86;
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#[cfg(target_arch = "x86_64")]
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use core::arch::x86_64 as x86;
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// SAFETY: Intrinsics covered by cfg
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unsafe {
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match N {
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#[cfg(target_feature = "neon")]
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8 => transize(vtbl1_u8, self, idxs),
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#[cfg(target_feature = "ssse3")]
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16 => transize(x86::_mm_shuffle_epi8, self, idxs),
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#[cfg(target_feature = "simd128")]
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16 => transize(wasm::i8x16_swizzle, self, idxs),
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#[cfg(all(target_arch = "aarch64", target_feature = "neon"))]
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16 => transize(vqtbl1q_u8, self, idxs),
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#[cfg(all(target_feature = "avx2", not(target_feature = "avx512vbmi")))]
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32 => transize_raw(avx2_pshufb, self, idxs),
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#[cfg(target_feature = "avx512vl,avx512vbmi")]
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32 => transize(x86::_mm256_permutexvar_epi8, self, idxs),
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// Notable absence: avx512bw shuffle
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// If avx512bw is available, odds of avx512vbmi are good
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// FIXME: initial AVX512VBMI variant didn't actually pass muster
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// #[cfg(target_feature = "avx512vbmi")]
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// 64 => transize(x86::_mm512_permutexvar_epi8, self, idxs),
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_ => {
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let mut array = [0; N];
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for (i, k) in idxs.to_array().into_iter().enumerate() {
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if (k as usize) < N {
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array[i] = self[k as usize];
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};
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}
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array.into()
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}
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}
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}
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}
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}
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/// "vpshufb like it was meant to be" on AVX2
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///
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/// # Safety
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/// This requires AVX2 to work
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#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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#[target_feature(enable = "avx2")]
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#[allow(unused)]
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#[inline]
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#[allow(clippy::let_and_return)]
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unsafe fn avx2_pshufb(bytes: Simd<u8, 32>, idxs: Simd<u8, 32>) -> Simd<u8, 32> {
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use crate::simd::SimdPartialOrd;
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#[cfg(target_arch = "x86")]
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use core::arch::x86;
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#[cfg(target_arch = "x86_64")]
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use core::arch::x86_64 as x86;
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use x86::_mm256_permute2x128_si256 as avx2_cross_shuffle;
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use x86::_mm256_shuffle_epi8 as avx2_half_pshufb;
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let mid = Simd::splat(16u8);
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let high = mid + mid;
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// SAFETY: Caller promised AVX2
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unsafe {
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// This is ordering sensitive, and LLVM will order these how you put them.
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// Most AVX2 impls use ~5 "ports", and only 1 or 2 are capable of permutes.
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// But the "compose" step will lower to ops that can also use at least 1 other port.
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// So this tries to break up permutes so composition flows through "open" ports.
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// Comparative benches should be done on multiple AVX2 CPUs before reordering this
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let hihi = avx2_cross_shuffle::<0x11>(bytes.into(), bytes.into());
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let hi_shuf = Simd::from(avx2_half_pshufb(
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hihi, // duplicate the vector's top half
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idxs.into(), // so that using only 4 bits of an index still picks bytes 16-31
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));
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// A zero-fill during the compose step gives the "all-Neon-like" OOB-is-0 semantics
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let compose = idxs.simd_lt(high).select(hi_shuf, Simd::splat(0));
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let lolo = avx2_cross_shuffle::<0x00>(bytes.into(), bytes.into());
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let lo_shuf = Simd::from(avx2_half_pshufb(lolo, idxs.into()));
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// Repeat, then pick indices < 16, overwriting indices 0-15 from previous compose step
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let compose = idxs.simd_lt(mid).select(lo_shuf, compose);
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compose
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}
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}
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/// This sets up a call to an architecture-specific function, and in doing so
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/// it persuades rustc that everything is the correct size. Which it is.
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/// This would not be needed if one could convince Rust that, by matching on N,
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/// N is that value, and thus it would be valid to substitute e.g. 16.
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///
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/// # Safety
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/// The correctness of this function hinges on the sizes agreeing in actuality.
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#[allow(dead_code)]
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#[inline(always)]
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unsafe fn transize<T, const N: usize>(
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f: unsafe fn(T, T) -> T,
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bytes: Simd<u8, N>,
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idxs: Simd<u8, N>,
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) -> Simd<u8, N>
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where
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LaneCount<N>: SupportedLaneCount,
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{
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let idxs = zeroing_idxs(idxs);
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// SAFETY: Same obligation to use this function as to use mem::transmute_copy.
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unsafe { mem::transmute_copy(&f(mem::transmute_copy(&bytes), mem::transmute_copy(&idxs))) }
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}
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/// Make indices that yield 0 for this architecture
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#[inline(always)]
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fn zeroing_idxs<const N: usize>(idxs: Simd<u8, N>) -> Simd<u8, N>
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where
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LaneCount<N>: SupportedLaneCount,
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{
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// On x86, make sure the top bit is set.
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#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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let idxs = {
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use crate::simd::SimdPartialOrd;
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idxs.simd_lt(Simd::splat(N as u8))
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.select(idxs, Simd::splat(u8::MAX))
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};
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// Simply do nothing on most architectures.
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idxs
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}
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/// As transize but no implicit call to `zeroing_idxs`.
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#[allow(dead_code)]
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#[inline(always)]
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unsafe fn transize_raw<T, const N: usize>(
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f: unsafe fn(T, T) -> T,
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bytes: Simd<u8, N>,
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idxs: Simd<u8, N>,
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) -> Simd<u8, N>
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where
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LaneCount<N>: SupportedLaneCount,
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{
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// SAFETY: Same obligation to use this function as to use mem::transmute_copy.
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unsafe { mem::transmute_copy(&f(mem::transmute_copy(&bytes), mem::transmute_copy(&idxs))) }
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}
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