rust/codegen at 94cc01af159e2c086eeca2c9bf16fd3e60f04f43 - rust

History

Jubilee 2f98dcf9ba Rollup merge of #131258 - taiki-e:s390x-stabilize-asm, r=Amanieu Stabilize s390x inline assembly This stabilizes inline assembly for s390x (SystemZ). Corresponding reference PR: https://github.com/rust-lang/reference/pull/1643 --- From the requirements of stabilization mentioned in https://github.com/rust-lang/rust/issues/93335 > Each architecture needs to be reviewed before stabilization: > - It must have clobber_abi. Done in https://github.com/rust-lang/rust/pull/130630. > - It must be possible to clobber every register that is normally clobbered by a function call. Done in the PR that added support for clobber_abi. > - Generally review that the exposed register classes make sense. The followings can be used as input/output: - `reg` (`r[0-10]`, `r[12-14]`): General-purpose register - `reg_addr` (`r[1-10]`, `r[12-14]`): General-purpose register except `r0` which is evaluated as zero in an address context This class is needed because `r0`, which may be allocated when using the `reg` class, cannot be used as a register in certain contexts. This is identical to the `a` constraint in LLVM and GCC. See https://github.com/rust-lang/rust/pull/119431 for details. - `freg` (`f[0-15]`): Floating-point register The followings are clobber-only: - `vreg` (`v[0-31]`): Vector register Technically `vreg` should be able to accept `#[repr(simd)]` types as input/output if the unstable `vector` target feature added is enabled, but `core::arch` has no s390x vector type and both `#[repr(simd)]` and `core::simd` are unstable. Everything related is unstable, so the fact that this is currently a clobber-only should not be considered a stabilization blocker. (https://github.com/rust-lang/rust/issues/130869 tracks unstable stuff here) - `areg` (`a[2-15]`): Access register All of the above register classes except `reg_addr` are needed for `clobber_abi`. The followings cannot be used as operands for inline asm (see also [getReservedRegs](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp#L258-L282) and [SystemZELFRegisters](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.h#L107-L128) in LLVM): - `r11`: frame pointer - `r15`: stack pointer - `a0`, `a1`: Reserved for system use - `c[0-15]` (control register) Reserved by the kernel Although not listed in the above requirements, `preserves_flags` is implemented in https://github.com/rust-lang/rust/pull/111331. --- cc ``@uweigand`` r? ``@Amanieu`` ``@rustbot`` label +O-SystemZ +A-inline-assembly		2024-11-09 20:28:43 -08:00
..
asm	Stabilize s390x inline assembly	2024-11-08 10:46:00 +09:00
auxiliary
avr	Rename Receiver -> LegacyReceiver	2024-10-22 12:55:16 +00:00
cffi	more `asm!` -> `naked_asm!` in tests	2024-10-06 18:12:25 +02:00
compiletest-self-test	tests/codegen: add `minicore` compiletest self-test	2024-10-31 18:20:11 +08:00
cross-crate-inlining
debug-accessibility
debuginfo-proc-macro	Add discriminators to DILocations when multiple functions are inlined into a single point.	2024-11-09 08:01:31 -08:00
dllimports
enum
float	x86-32 float return for 'Rust' ABI: treat all float types consistently	2024-10-20 11:41:08 +02:00
instrument-coverage
instrument-xray
intrinsics	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
issues	Add a Few Codegen Tests	2024-11-02 05:33:56 +00:00
lib-optimizations
loongarch-abi
macos
meta-filecheck
naked-fn
non-terminate
patchable-function-entry
remap_path_prefix
repr	Remove the `wasm32-wasi` target from rustc	2024-11-03 07:09:34 -08:00
riscv-abi
sanitizer	Rollup merge of #130225 - adetaylor:rename-old-receiver, r=wesleywiser	2024-10-24 14:19:53 +11:00
simd
simd-intrinsic	Update test for LLVM 20's new vector splat syntax	2024-11-07 20:02:20 +01:00
src-hash-algorithm
unwind-abis
aarch64-struct-align-128.rs
abi-efiapi.rs
abi-main-signature-16bit-c-int.rs
abi-main-signature-32bit-c-int.rs
abi-repr-ext.rs
abi-sysv64.rs
abi-x86_64_sysv.rs
abi-x86-interrupt.rs
addr-of-mutate.rs
adjustments.rs
align-byval-alignment-mismatch.rs
align-byval-vector.rs
align-byval.rs
align-enum.rs
align-fn.rs
align-offset.rs
align-struct.rs
alloc-optimisation.rs
array-clone.rs
array-cmp.rs
array-codegen.rs
array-equality.rs
array-from_fn.rs
array-map.rs
array-optimized.rs
array-repeat.rs
ascii-char.rs
async-closure-debug.rs
async-fn-debug-awaitee-field.rs
async-fn-debug-msvc.rs
async-fn-debug.rs
atomic-operations.rs
atomicptr.rs	move strict provenance lints to new feature gate, remove old feature gates	2024-10-21 15:22:17 +01:00
autovectorize-f32x4.rs
binary-heap-peek-mut-pop-no-panic.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
binary-search-index-no-bound-check.rs
bool-cmp.rs
box-uninit-bytes.rs
bpf-alu32.rs
branch-protection-old-llvm.rs
branch-protection.rs	rustc_codegen_llvm: Add a new 'pc' option to branch-protection	2024-10-31 11:59:17 +00:00
call-llvm-intrinsics.rs
call-metadata.rs
cast-optimized.rs
cast-target-abi.rs
catch-unwind.rs
cdylib-external-inline-fns.rs
cf-protection.rs
cfguard-checks.rs
cfguard-disabled.rs
cfguard-nochecks.rs
cfguard-non-msvc.rs
char-ascii-branchless.rs
checked_ilog.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
checked_math.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
clone_as_copy.rs	Mark `simplify_aggregate_to_copy` mir-opt as unsound	2024-10-31 13:48:06 +08:00
clone-shims.rs
codemodels.rs
coercions.rs
cold-call-declare-and-call.rs
common_prim_int_ptr.rs
comparison-operators-2-tuple.rs
comparison-operators-newtype.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
const_scalar_pair.rs
const-vector.rs
constant-branch.rs
consts.rs
coroutine-debug-msvc.rs
coroutine-debug.rs
dealloc-no-unwind.rs
debug-alignment.rs
debug-column-msvc.rs
debug-column.rs
debug-compile-unit-path.rs
debug-fndef-size.rs
debug-limited.rs
debug-line-directives-only.rs
debug-line-tables-only.rs
debug-linkage-name.rs
debug-vtable.rs
debuginfo-constant-locals.rs
debuginfo-generic-closure-env-names.rs
debuginfo-inline-callsite-location.rs
deduced-param-attrs.rs
default-requires-uwtable.rs
default-visibility.rs	Use Default visibility for rustc-generated C symbol declarations	2024-10-11 08:43:27 +11:00
direct-access-external-data.rs
dont_codegen_private_const_fn_only_used_in_const_eval.rs
drop-in-place-noalias.rs
drop.rs
dst-offset.rs
dst-vtable-align-nonzero.rs
dst-vtable-size-range.rs
ehcontguard_disabled.rs
ehcontguard_enabled.rs
emcripten-catch-unwind.rs
enable-lto-unit-splitting.rs
error-provide.rs
export-no-mangle.rs
external-no-mangle-fns.rs
external-no-mangle-statics.rs
fastcall-inreg.rs
fatptr.rs
fewer-names.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
fixed-x18.rs
float_math.rs
fn-impl-trait-self.rs
force-frame-pointers.rs
force-no-unwind-tables.rs
force-unwind-tables.rs
frame-pointer.rs
function-arguments-noopt.rs
function-arguments.rs	pointee_info_at: fix logic for recursing into enums	2024-11-08 07:35:29 +01:00
function-return.rs
gdb_debug_script_load.rs
generic-debug.rs
i128-x86-align.rs	Return values larger than 2 registers using a return area pointer	2024-10-10 14:24:43 +00:00
infallible-unwrap-in-opt-z.rs
inherit_overflow.rs
inline-always-works-always.rs
inline-debuginfo.rs
inline-function-args-debug-info.rs
inline-hint.rs
instrument-mcount.rs
integer-cmp.rs
integer-overflow.rs
internalize-closures.rs
intrinsic-no-unnamed-attr.rs
is_val_statically_known.rs
issue-97217.rs
iter-repeat-n-trivial-drop.rs	llvm: Tolerate propagated range metadata	2024-10-16 18:38:26 +00:00
layout-size-checks.rs
lifetime_start_end.rs
link_section.rs
link-dead-code.rs
llvm_module_flags.rs
llvm-ident.rs
loads.rs
local-generics-in-exe-internalized.rs
lto-removes-invokes.rs
mainsubprogram.rs
mainsubprogramstart.rs
match-optimized.rs
match-optimizes-away.rs
match-unoptimized.rs
maybeuninit-rvo.rs
mem-replace-big-type.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
mem-replace-simple-type.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
merge-functions.rs
method-declaration.rs
mir_zst_stores.rs
mir-aggregate-no-alloca.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
mir-inlined-line-numbers.rs
move-before-nocapture-ref-arg.rs
move-operands.rs
naked-asan.rs	various fixes for `naked_asm!` implementation	2024-10-06 19:00:09 +02:00
no_builtins-at-crate.rs
no-alloca-inside-if-false.rs
no-assumes-on-casts.rs
no-dllimport-w-cross-lang-lto.rs
no-jump-tables.rs
no-plt.rs
no-redundant-item-monomorphization.rs
noalias-box-off.rs
noalias-box.rs
noalias-flag.rs
noalias-freeze.rs
noalias-refcell.rs
noalias-rwlockreadguard.rs
noalias-unpin.rs
noreturn-uninhabited.rs
noreturnflag.rs
nounwind.rs
nrvo.rs
optimize-attr-1.rs
option-as-slice.rs	Add precondition checks to ptr::offset, ptr::add, ptr::sub	2024-10-07 11:12:58 -04:00
option-niche-eq.rs
overaligned-constant.rs
packed.rs
panic-abort-windows.rs
panic-in-drop-abort.rs
panic-unwind-default-uwtable.rs
pattern_type_symbols.rs
personality_lifetimes.rs
pgo-counter-bias.rs
pgo-instrumentation.rs
pic-relocation-model.rs
pie-relocation-model.rs
placement-new.rs	add codegen test	2024-10-22 02:25:38 -07:00
powerpc64le-struct-align-128.rs
precondition-checks.rs
ptr-arithmetic.rs
ptr-read-metadata.rs
range-attribute.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
README.md
refs.rs
regparm-inreg.rs	compiler: Revert -Zregparm handling for extern Rust	2024-10-18 11:59:20 -07:00
repeat-trusted-len.rs
riscv-target-abi.rs	Always specify `llvm_abiname` for RISC-V targets	2024-10-17 02:07:02 +01:00
rust-abi-arch-specific-adjustment.rs	Set `signext` or `zeroext` for integer arguments on LoongArch64	2024-10-23 04:42:21 +02:00
scalar-pair-bool.rs
set-discriminant-invalid.rs
skip-mono-inside-if-false.rs
slice_as_from_ptr_range.rs
slice-as_chunks.rs
slice-indexing.rs
slice-init.rs
slice-iter-fold.rs
slice-iter-len-eq-zero.rs
slice-iter-nonnull.rs
slice-pointer-nonnull-unwrap.rs
slice-position-bounds-check.rs
slice-ref-equality.rs
slice-reverse.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
slice-windows-no-bounds-check.rs
some-abis-do-extend-params-to-32-bits.rs
some-global-nonnull.rs
sparc-struct-abi.rs
split-lto-unit.rs
sroa-fragment-debuginfo.rs
sse42-implies-crc32.rs
stack-probes-inline.rs
stack-protector.rs
static-relocation-model-msvc.rs
staticlib-external-inline-fns.rs
step_by-overflow-checks.rs
stores.rs
swap-large-types.rs
swap-small-types.rs
target-cpu-on-functions.rs
target-feature-inline-closure.rs
target-feature-overrides.rs
thread-local.rs
tied-features-strength.rs
to_vec.rs
trailing_zeros.rs
transmute-optimized.rs
transmute-scalar.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
try_question_mark_nop.rs	try_question_mark_nop: update test for LLVM 20	2024-11-08 10:43:06 -05:00
tune-cpu-on-functions.rs
tuple-layout-opt.rs	Fix test expectations for 32bit x86	2024-10-19 13:09:21 +00:00
ub-checks.rs
unchecked_shifts.rs
unchecked-float-casts.rs
uninit-consts.rs
union-abi.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
unwind-and-panic-abort.rs
unwind-extern-exports.rs
unwind-extern-imports.rs
unwind-landingpad-cold.rs
unwind-landingpad-inline.rs
used_with_arg.rs
var-names.rs	Set `signext` or `zeroext` for integer arguments on RISC-V	2024-10-23 04:42:03 +02:00
vec_pop_push_noop.rs
vec-as-ptr.rs
vec-calloc.rs
vec-in-place.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
vec-iter-collect-len.rs
vec-iter.rs
vec-len-invariant.rs
vec-optimizes-away.rs
vec-reserve-extend.rs
vec-shrink-panik.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
vec-with-capacity.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
vecdeque_no_panic.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
vecdeque_pop_push.rs
vecdeque-drain.rs	tests: `ignore-debug` -> `ignore-std-debug-assertions`	2024-10-31 17:33:42 +08:00
vecdeque-nonempty-get-no-panic.rs
virtual-function-elimination-32bit.rs
virtual-function-elimination.rs
vtable-loads.rs
vtable-upcast.rs
wasm_casts_trapping.rs
wasm_exceptions.rs
zip.rs
zst-offset.rs

README.md

The files here use the LLVM FileCheck framework, documented at https://llvm.org/docs/CommandGuide/FileCheck.html.

One extension worth noting is the use of revisions as custom prefixes for FileCheck. If your codegen test has different behavior based on the chosen target or different compiler flags that you want to exercise, you can use a revisions annotation, like so:

// revisions: aaa bbb
// [bbb] compile-flags: --flags-for-bbb

After specifying those variations, you can write different expected, or explicitly unexpected output by using <prefix>-SAME: and <prefix>-NOT:, like so:

// CHECK: expected code
// aaa-SAME: emitted-only-for-aaa
// aaa-NOT:                        emitted-only-for-bbb
// bbb-NOT:  emitted-only-for-aaa
// bbb-SAME:                       emitted-only-for-bbb